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參數(shù)資料
| 型號： | KMC8610VT1333JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 75/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HOST PROCESS 1333MHZ 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.025V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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Hardware Design Considerations
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
77
Note the following:
SDnAVDD should be a filtered version of SVDD.
Signals on the SerDes interface are fed from the SVDD power plane.
3.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC8610 system, and the device itself requires a clean, tightly regulated source of power. Therefore,
it is recommended that the system designer place at least one decoupling capacitor at each VDD, BVDD, OVDD, GVDD,
VDD_Core, and VDD_PLAT pin of the device. These decoupling capacitors should receive their power from separate VDD,
BVDD, OVDD, GVDD, VDD_Core, VDD_PLAT, and GND power planes in the PCB, utilizing short traces to minimize
inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, BVDD,
OVDD, GVDD, VDD_Core, and VDD_PLAT planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
3.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SnVDD and XnVDD) to ensure low jitter on transmit and
reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
device as close to the supply and ground connections as possible.
Second, there should be a 1-F ceramic chip capacitor on each side of the device. This should be done for all SerDes
supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low equivalent series resistance
(ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip capacitor. This should be done for all
SerDes supplies.
3.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to VDD, BVDD, OVDD, GVDD, VDD_Core, VDD_PLAT, XnVDD, and SnVDD as required. All unused
active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground
connections must be made to all external VDD, BVDD, OVDD, GVDD, VDD_Core, VDD_PLAT, XnVDD, SnVDD, and GND pins
of the device.
Special cases:
Local Bus—If parity is not used, tie LDP[0:3] to ground via a 4.7-k
Ω resistor, tie LPBSE to OV
DD via a 4.7-kΩ resistor
(pull-up resistor). For systems which boot from local bus (GPCM)-controlled Flash, a pull up on LGPL4 is required.
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