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參數(shù)資料
| 型號： | KMC8610VT1333JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 54/96頁 |
| 文件大小： | 0K |
| 描述： | IC HOST PROCESS 1333MHZ 783-PBGA |
| 標準包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.025V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
58
2.17.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed current steering
logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may
need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled
connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output
first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling.
NOTE
chip's internal structure, output impedance and termination requirements are different
between various clock driver chip manufacturers, it is very possible that the clock circuit
reference designs provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore, Freescale
Semiconductor can neither provide the optimal clock driver reference circuits nor
guarantee the correctness of the following clock driver connection reference circuits. The
system designer is recommended to contact the selected clock driver chip vendor for the
optimal reference circuits with the MPC8610 SerDes reference clock receiver requirement
provided in this document.
Figure 34 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC
levels of the clock driver chip is compatible with MPC8610 SerDes reference clock input’s DC requirement.
Figure 34. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 35 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock
driver’s common mode voltage is higher than the MPC8610 SerDes reference clock input’s allowed range (100 to 400 mV),
AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-
Ω termination resistor. It also
assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external
component.
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω Differential PWB Trace
Clock driver vendor dependent
source termination resistor
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
MPC8610
CLK_Out
SerDes Refer.
CLK Receiver
Clock Driver
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