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參數(shù)資料
| 型號： | KMC8610VT1333JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 52/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HOST PROCESS 1333MHZ 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.025V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
56
SerDes reference clock receiver reference circuit structure
—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 30.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-
Ω termination to SGND followed by
on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle
can be produced by a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage
at 400 mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50
Ω to SGND DC, or it
exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 30. Receiver of SerDes Reference Clocks
2.17.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8610 SerDes reference clock inputs is different depending on the signaling mode used
to connect the clock driver chip and SerDes reference clock inputs as described below.
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential peak-peak (or
between 200 and 800 mV differential peak). In other words, each signal wire of the differential pair must have a
single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-
or AC-coupled connection.
— For external DC-coupled connection, as described in Section 2.17.2.1, “SerDes Reference Clock Receiver
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 and 400 mV. Figure 31 shows the SerDes reference clock input requirement for
DC-coupled connection scheme.
Input
Amp
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
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