參數(shù)資料
型號(hào)： KSZ8863MLL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 27/106頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863MLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863MLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3751-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3577-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱： 576-3867
PIC16C72 Series
DS39016A-page 26
Preliminary
1998 Microchip Technology Inc.
4.2.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the y” during program
execution.
4.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overows from FFh to 00h. This overow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 4-1
REGISTERS ASSOCIATED WITH TIMER0
Note:
To avoid an unintended device RESET, a
specic instruction sequence (shown in the
PICmicro Mid-Range MCU Reference
Manual, DS3023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must be
followed even if the WDT is disabled.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
01h,101h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
81h,181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
85h
TRISA
—
PORTA Data Direction Register
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (=Fosc/4)
SYNC
2
Cycles
TMR0 reg
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
0
1
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
1
0
1
Data Bus
Set ag bit T0IF
on Overow
8
PSA
T0CS
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