參數(shù)資料
型號： KSZ8863MLL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 45/106頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863MLL
標準包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863MLL
已供物品： 板
相關產(chǎn)品： 576-3751-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3577-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱： 576-3867
PIC16C72 Series
DS39016A-page 42
Preliminary
1998 Microchip Technology Inc.
8.2.1
OPERATION OF SSP MODULE IN SPI
MODE - PIC16C72
A block diagram of the SSP Module in SPI Mode is
shown in Figure 8-3.
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
Serial Data Out (SDO)
RC5/SDO
Serial Data In (SDI)
RC4/SDI/SDA
Serial Clock (SCK)
RC3/SCK/SCL
Additionally a fourth pin may be used when in a slave
mode of operation:
Slave Select (SS)
RA5/SS/AN4
When initializing the SPI, several options need to be
specied. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specied:
Master Operation (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Output/Input data on the Rising/
Falling edge of SCK)
Clock Rate (master operation only)
Slave Select Mode (Slave mode only)
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or recongure SPI
mode, clear enable bit SSPEN, re-initialize SSPCON
register, and then set enable bit SSPEN. This cong-
ures the SDI, SDO, SCK, and SS pins as serial port
pins. For the pins to behave as the serial port function,
they must have their data direction bits (in the TRIS reg-
ister) appropriately programmed. That is:
SDI must have TRISC<4> set
SDO must have TRISC<5> cleared
SCK (master operation) must have TRISC<3>
cleared
SCK (Slave mode) must have TRISC<3> set
SS must have TRISA<5> set (if implemented)
FIGURE 8-3:
SSP BLOCK DIAGRAM
(SPI MODE)
TABLE 8-1
REGISTERS ASSOCIATED WITH SPI OPERATION
Read
Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0
shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
(1)
ADIE
(1)
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV SSPEN
CKP
SSPM3 SSPM2
SSPM1
SSPM0
0000 0000
85h
TRISA
—
PORTA Data Direction Register
--11 1111
94h
SSP-
STAT
—
D/A
P
S
R/W
UA
BF
--00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1:
These bits are unimplemented, read as '0'.
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