- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16817 > KSZ8863MLL-EVAL (Micrel Inc)BOARD EVALUATION FOR KSZ8863MLL PDF資料下載
參數(shù)資料
| 型號： | KSZ8863MLL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 50/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8863MLL |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng) PHY |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8863MLL |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-3751-ND - IC ETHERNET SWITCH 3PORT 48-LQFP 576-3577-ND - IC ETHERNET SW 3PORT 48-LQFP |
| 其它名稱： | 576-3867 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 47
8.4
SSP I2C Operation
The SSP module in I2C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
rmware implementations of the master functions. The
SSP module implements the standard mode specica-
tions as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
congure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 8-7:
SSP BLOCK DIAGRAM
(I2C MODE)
The SSP module has ve registers for I2C operation.
These are the:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly acces-
sible
SSP Address Register (SSPADD)
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Slave mode (7-bit address), with start and
stop bit interrupts enabled
I2C Slave mode (10-bit address), with start and
stop bit interrupts enabled
I2C Firmware controlled master operation, slave
is idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I2C operation may be
found in the PICmicro Mid-Range MCU Reference
Manual, DS33023.
8.4.1
SLAVE MODE
In slave mode, the SCL and SDA pins must be cong-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b)
The overow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 8-3 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specication as well as the requirement of the SSP
module is shown in timing parameter #100 and param-
eter #101.
Read
Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
data bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
shift
clock
MSb
SDI/
LSb
SDA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V150B36E150BL | CONVERTER MOD DC/DC 36V 150W |
| 50PX47MEFCTA6.3X11 | CAP ALUM 47UF 50V 20% RADIAL |
| IR3084UMTRPBF | IC CTLR XPHASE 28-MLPQ |
| 202D296-25-0 | BOOT MOLDED |
| 1812R-104J | INDUCTOR UNSHIELDED 100UH SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8863MLLI | 功能描述:以太網(wǎng) IC 3-Port Copper 10/100 Ethernet Switch w/ 1x MII Interface (Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8863RLL | 功能描述:以太網(wǎng) IC 3-Port Copper 10/100 Ethernet Switch with 1x RMII Interface (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8863RLL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 3-Port Copper 10/100 Ethernet Switch with 1x RMII Interface - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8863RLLI | 功能描述:以太網(wǎng) IC 3-Port Copper 10/100 Ethernet Switch w/ 1x RMII Interface (Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8864CNXCA | 功能描述:Ethernet Controller 10/100 Base-T/TX PHY MII, RMII Interface 64-QFN (8x8) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:控制器 接口:MII，RMII 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:- 工作溫度:0°C ~ 70°C 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN（8x8） 標(biāo)準(zhǔn)包裝:348 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。