參數(shù)資料
型號: KSZ8863MLL-EVAL
廠商: Micrel Inc
文件頁數(shù): 92/106頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8863MLL
標準包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8863MLL
已供物品:
相關(guān)產(chǎn)品: 576-3751-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3577-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱: 576-3867
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 85
FIGURE 13-3: CLKOUT AND I/O TIMING
TABLE 13-4
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
10*
TosH2ckL
OSC1
↑ to CLKOUT↓
75
200
ns
Note 1
11*
TosH2ckH
OSC1
↑ to CLKOUT↑
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT
↓ to Port out valid
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT
TOSC + 200
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT
0
ns
Note 1
17*
TosH2ioV
OSC1
↑ (Q1 cycle) to Port out valid
50
150
ns
18*
TosH2ioI
OSC1
↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C72/CR72
100
ns
PIC16LC72/LCR72
200
ns
19*
TioV2osH
Port input valid to OSC1
↑ (I/O in setup time)
0
ns
20*
TioR
Port output rise time
PIC16C72/CR72
10
40
ns
PIC16LC72/LCR72
80
ns
21*
TioF
Port output fall time
PIC16C72/CR72
10
40
ns
PIC16LC72/LCR72
80
ns
22*
Tinp
INT pin high or low time
TCY
ns
23*
Trbp
RB7:RB4 change INT high or low time
TCY
ns
*
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
These parameters are asynchronous events not related to any internal clock edges.
Note 1:
Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 13-1 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4
Q1
Q2
Q3
10
13
14
17
20, 21
19
18
15
11
12
16
old value
new value
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