80h(1) INDF Addressi" />
參數(shù)資料
型號(hào)： KSZ8863MLL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 86/106頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR KSZ8863MLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863MLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3751-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3577-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱： 576-3867
PIC16C72 Series
DS39016A-page 8
Preliminary
1998 Microchip Technology Inc.
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
—
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h
—
Unimplemented
—
89h
—
Unimplemented
—
8Ah(1,2)
PCLATH
—
Write Buffer for the upper 5 bits of the PC
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
—
ADIE
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
8Dh
—
Unimplemented
—
8Eh
PCON
—
POR
BOR
---- --qq
---- --uu
8Fh
—
Unimplemented
—
90h
—
Unimplemented
—
91h
—
Unimplemented
—
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP(5)
CKE(5)
D/A
P
S
R/W
UA
BF
0000 0000
95h
—
Unimplemented
—
96h
—
Unimplemented
—
97h
—
Unimplemented
—
98h
—
Unimplemented
—
99h
—
Unimplemented
—
9Ah
—
Unimplemented
—
9Bh
—
Unimplemented
—
9Ch
—
Unimplemented
—
9Dh
—
Unimplemented
—
9Eh
—
Unimplemented
—
9Fh
ADCON1
—
PCFG2
PCFG1
PCFG0
---- -000
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5:
SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
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