參數(shù)資料
型號(hào): KSZ8863MLL-EVAL
廠商: Micrel Inc
文件頁數(shù): 93/106頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8863MLL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8863MLL
已供物品:
相關(guān)產(chǎn)品: 576-3751-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3577-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱: 576-3867
PIC16C72 Series
DS39016A-page 86
Preliminary
1998 Microchip Technology Inc.
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 13-5: BROWN-OUT RESET TIMING
TABLE 13-5
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
s
VDD = 5V, -40C to +125C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40C to +125C
32
Tost
Oscillation Start-up Timer Period
1024TOSC
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40C to +125C
34
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
2.1
s
35
TBOR
Brown-out Reset pulse width
100
s
VDD
≤ BVDD (D005)
*
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 13-1 for load conditions.
VDD
BVDD
35
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