參數(shù)資料
型號: L64781
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 10/164頁
文件大?。?/td> 2003K
代理商: L64781
Demod Parameters Registers
5-37
5.5.12 Demod Parameters Register 15 (0x15)
This is an 8-bit wide, read/write register.
0
Set these bits to 0.
D[7:3]
TIM_IIR_GAIN Timing IIR Filter Gain
D[2:0] R/W
These bits govern the amount of IIR ltering performed in
the timing loop lter.
The initial value of TIM_IIR_GAIN is 011.
5.5.13 Digital Timing Recovery (DTR) Loop
If the analog timing recovery loop is in use, the digital timing recovery
(DTR) must be disabled; if the DTR is enabled, the DTR_INIT_FREQ
(addresses 0x16, 0x17, 0x18) and DTR_SENSITIVITY (address 0x19)
must be set to the correct values. These values depend on the channel
bandwidth and the frequency of the crystal. This section describes how
to program these registers.
The DTR_INIT_FREQ, Figure 5.4, is the base frequency offset of the
theoretical sampling frequency. It represents the step that is added to the
accumulator every cycle. This accumulator contents give the position of
the resampling instant relative to the most recent clock edge.
D7
D6
D5
D4
D3
D2
D0
00000
TIM_IIR_GAIN
TIM_IIR_GAIN[2:0]
Denition
0
Gain 0 = 1/16
0
1
Gain 1 = 1/32
0
1
0
Gain 2 = 1/64
0
1
Gain 3 = 1/128
0
Gain 4 = 1/256
0
1
Gain 5 = 1/512
0
1
0
Gain 6 = 1/1024
0
1
Gain 7 = 1/2048
l64781.book Page 37 Friday, January 19, 2001 1:28 PM
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