參數(shù)資料
型號(hào)： LH28F040SUTD-Z4
廠商： Sharp Corporation
英文描述： 4M (512K 】 8) Flash Memory
中文描述： 4分（為512k】8）閃存
文件頁(yè)數(shù)： 15/32頁(yè)
文件大小： 247K
代理商： LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
15
Figure 9. Two-Byte Serial Writes with Compatible Status Registers
START
BUS
OPERATION
COMMAND
COMMENTS
CSR.7 =
0
1
OPERATION COMPLETE
Read
Write
Write
2-Byte
Write
Q = CSRD
Toggle BE
0
, BE
1
or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Q = CSRD
Toggle BE
0
, BE
1
or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
D = WD
A
= 0 loads low byte
of Data Register.
A
= 1 loads high byte
of Data Register.
Other Addresses = X
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Cycle notes for description of codes.
D = FBH
A = X
Write
D = WD
A = WA
Internally, A
is automatically
complemented to load the
alternate byte location of the
Data Register.
Read
28F040SUZ4-9
READ COMPATIBLE
STATUS REGISTER
WRITE FBH
WRITE DATA/A
0
CSR.7 =
CSR.4, 5 =
1
0
1
0
ANOTHER
2-BYTE
WRITE
NO
YES
(NOTE)
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
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