參數(shù)資料
型號(hào)： LH28F040SUTD-Z4
廠商： Sharp Corporation
英文描述： 4M (512K 】 8) Flash Memory
中文描述： 4分（為512k】8）閃存
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 247K
代理商： LH28F040SUTD-Z4
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
20
Timing Nomenclature
For 3.3 V systems use 1.5 V cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
t
CE
t
OE
t
ACC
t
AVQV
t
AS
t
DH
t
ELQV
t
GLQV
time (t) from BE
(E) going low (L) to the outputs (Q) becoming valid (V)
time (t) from OE
(G) going low (L) to the outputs (Q) becoming valid (V)
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
t
AVWH
t
WHDX
time (t) from address (A) valid (V) to WE
(W) going high (H)
time (t) from WE
(W) going high (H) to when the data (D) can become undefined (X)
Figure 13. Transient Input/Output
Reference Waveform (V
CC
= 3.3 V)
Figure 14. Transient Equivalent Testing
Load Circuit (V
CC
= 3.3 V)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
BE
(Byte Enable)
1
X
Driven, but not necessarily valid
G
OE
(Output Enable)
Z
High Impedance
W
WE (Write Enable)
V
Any Voltage Level
3 V
V
CC
at 3.0 V Min.
NOTE:
1. BE
X
means either BE
0
or BE
1
.
INPUT
0.0
TEST POINTS
OUTPUT
3.0
1.5
1.5
28F040SUZ4-13
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1'
and 0.0 V for a Logic '0'. Input timing begins
and output timing ends at 1.5 V. Input rise
and fall times (10% to 90%) < 10 ns.
2.5 ns OF 50
TRANSMISSION LINE
TOTAL CAPACITANCE = 50 pF
FROM OUTPUT
UNDER TEST
TEST
POINT
28F040SUZ4-14
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