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參數(shù)資料
| 型號： | LH28F040SUTD-Z4 |
| 廠商： | Sharp Corporation |
| 英文描述： | 4M (512K 】 8) Flash Memory |
| 中文描述： | 4分（為512k】8）閃存 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 247K |
| 代理商： | LH28F040SUTD-Z4 |
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LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
26
AC Characteristics for WE
- Controlled Command Write Operations
1
V
CC
= 3.25 V ± 0.35 V, T
A
= -20°C to +70°C
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE
for all Command Write operations.
7. The maximum value of byte write time is the maximum write time inside the chip. It is not the time until the whole
writing procedure is completed properly. It is necessary to check CSR to see if the writing procedure is properly
completed.
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
t
AVAV
Write Cycle Time
150
ns
t
VPWH
V
PP
Set up to WE Going High
100
ns
3
t
ELWL
BE
0
and BE
1
Setup to WE Going Low
0
ns
t
AVWH
Address Setup to WE Going High
110
ns
2, 6
t
DVWH
Data Setup to WE Going High
110
ns
2, 6
t
WLWH
WE Pulse Width
110
ns
t
WHDX
Data Hold from WE High
10
ns
2
t
WHAX
Address Hold from WE High
10
ns
2
t
WHEH
BE
0
and BE
1
Hold from WE High
10
ns
t
WHWL
WE Pulse Width High
75
ns
t
GHWL
Read Recovery before Write
0
ns
t
WHGL
Write Recovery before Read
120
ns
t
QVVL
t
WHQV1
t
WHQV2
V
PP
Hold from Valid Status Register Data
0
μs
Duration of Byte Write Operation
20
8
250
μs
4, 5, 7
Duration of Block Erase Operation
0.3
s
4
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