參數(shù)資料
型號(hào)： LU3X31T-T64
英文描述： LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX
中文描述： LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州
文件頁(yè)數(shù)： 10/44頁(yè)
文件大?。?/td> 580K
代理商： LU3X31T-T64
10
Lucent Technologies Inc.
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description
The LU3X31T-T64 integrates a 100Base-X physical
sublayer (PHY), a 100Base-TX physical medium
dependent (PMD) transceiver, and a complete 10Base-
T module into a single chip for both 10 Mbits/s and
100 Mbits/s Ethernet operation. This device provides
an IEEE802.3u compliant media independent interface
(MII) to communicate between the physical signaling
and the medium access control (MAC) layers for both
100Base-X and 10Base-T operations. The device is
capable of operating in either full-duplex mode or half-
duplex mode in either 10 Mbits/s or 100 Mbits/s opera-
tion. Operational modes can be selected by hardware
configuration pins, selected by software settings of
management registers, or determined by the on-chip
autonegotiation logic.
The 10Base-T section of the device consists of the
10 Mbits/s transceiver module with filters and a
Manchester ENDEC module.
The 100Base-X section of the device implements the
following functional blocks:
I
100Base-X physical coding sublayer (PCS)
I
100Base-X physical medium attachment (PMA)
I
Twisted-pair transceiver
The 100Base-X and 10Base-T sections share the fol-
lowing functional blocks:
I
Clock synthesizer module (CSM)
I
MII registers
I
IEEE 802.3u autonegotiation
Each of these functional blocks is described below.
Media Independent Interface (MII)
The LU3X31T-T64 implements an IEEE802.3u Clause
22 compliant MII as described below.
Interface Signals
Transmit Data Interface.
The MII transmit data inter-
face comprises seven signals: TXD[3:0] are the nibble
size data path, TXEN signals the presence of data on
TXD, TXER indicates that a transmit coding error has
occurred, and TXCLK is the transmit clock that syn-
chronizes all the transmit signals. TXCLK is supplied by
the on-chip clock synthesizer.
Receive Data Interface.
The MII receive data interface
comprises seven signals: RXD[3:0] are the nibble size
data path, RXDV signals the presence of data on RXD,
RXER indicates a received coding error, and RXCLK is
the receive clock. Depending upon the operation mode,
RXCLK is generated by the clock recovery module of
either the 100Base-X or 10Base-T receiver.
Status Interface.
Two status signals, COL and CRS,
are generated in the LU3X31T-T64 to indicate collision
status and carrier sense status to the MAC. COL is
asserted asynchronously whenever LU3X31T-T64 is
transmitting and receiving at the same time in a half-
duplex operation mode. In the full-duplex mode, COL is
inactive. CRS is asserted asynchronously whenever
there is activity on either the transmitter or the receiver.
In full-duplex mode, CRS is asserted only when there is
activity on the receiver.
Operation Modes
The LU3X31T-T64 supports three operation modes
and an isolate mode as described below.
100 Mbits/s Mode.
For 100 Mbits/s operation, the MII
operates in nibble mode with a clock rate of 25 MHz. In
normal operation, the MII data at RXD[3:0] and
TXD[3:0] are 4 bits wide. In bypass mode (either
BYP_4B5B or BYP_ALIGN option selected), the MII
data takes the form of 5-bit code-groups. The least sig-
nificant 4 bits appear on TXD[3:0] and RXD[3:0] as
usual, and the most significant bits (TXD[4] and
RXD[4]) appear on the TXER and RXER pins, respec-
tively.
10 Mbits/s Mode.
For 10 Mbits/s operation, the TXCLK
and RXCLK operate at 2.5 MHz. The data paths are
always 4 bits wide using TXD[3:0] and RXD[3:0] signal
lines.
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