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參數(shù)資料
| 型號： | LU3X31T-T64 |
| 英文描述： | LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| 中文描述： | LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州 |
| 文件頁數(shù)： | 11/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
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Lucent Technologies Inc.
11
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description
(continued)
MII Isolate Mode.
The LU3X31T-T64 implements an
MII isolate mode that is controlled by bit 10 of the con-
trol register (register 0h). The LU3X31T-T64 will set this
bit to one if the PHY address is set to 00000 upon pow-
erup/hardware reset. Otherwise, the LU3X31T-T64 will
initialize this bit to 0. Setting this bit to a 1 will put the
LU3X31T-T64 into isolate mode.
The isolate mode can also be activated by setting the
PHY address (bits 15 through 11 of register 19h) to 0
through the serial management interface, although the
content of the isolate register is not affected by the
modification of PHY address.
The LU3X31T-T64 does not respond to packet data
present at TXD[3:0], TXEN, and TXER inputs and pre-
sents a high impedance on the TXCLK, RXCLK, RXDV,
RXER, RXD[3:0], COL, and CRS outputs. The
LU3X31T-T64 will continue to respond to all manage-
ment transactions.
Serial Management Interface
The serial management interface (SMI) is the part of
the MII that is used to control and monitor status of the
LU3X31T-T64. This mechanism corresponds to the MII
specification for 100Base-X (Clause 22) and supports
registers 0 through 6. Additional vendor-specific regis-
ters are implemented within the range of 16 to 31. All
the registers are described in MII Registers on page 21
of this data sheet.
Management Register Access.
The SMI consists of
two pins, management data clock (MDC) and manage-
ment data input/output (MDIO). The LU3X31T-T64 is
designed to support an MDC frequency ranging up to
the IEEE specification of 2.5 MHz. The MDIO line is bi-
directional and may be shared by up to 32 devices.
The MDIO pin requires a 1.5 k
pull-up resistor which,
during IDLE and turnaround periods, will pull MDIO to
a logic 1 state. Each MII management data frame is
64 bits long. The first 32 bits are preamble consisting of
32 contiguous logic 1 bits on MDIO and 32 correspond-
ing cycles on MDC. Following preamble is the start-of-
frame field indicated by a <01> pattern. The next field
signals the operation code (OP): <10> indicates READ
from MII management register operation, and <01>
indicates WRITE to MII management register opera-
tion. The next two fields are PHY device address and
MII management register address. Both of them are
5 bits wide, and the most significant bit is transferred
first.
During READ operation, a 2-bit turnaround (TA) time
spacing between register address field and data field is
provided for the MDIO to avoid contention. Following
the turnaround time, a 16-bit data stream is read from
or written into the MII management registers of the
LU3X31T-T64.
The LU3X31T-T64 supports a preamble suppression
mode as indicated by a 1 in bit 6 of the basic mode sta-
tus register (BMSR, address 01h). If the station man-
agement entity (i.e., MAC or other management
controller) determines that all PHYs in the system sup-
port preamble suppression by returning a 1 in this bit,
then the station management entity need not generate
preamble for each management transaction. The
LU3X31T-T64 requires a single initialization sequence
of 32 bits of preamble following powerup/hardware
reset. This requirement is generally met by the manda-
tory pull-up resistor on MDIO or the management
access made to determine whether preamble suppres-
sion is supported. While the LU3X31T-T64 will respond
to management accesses without preamble, a mini-
mum of one idle bit between management transactions
is required as specified in IEEE 802.3u.
The PHY device address for LU3X31T-T64 is stored in
the PHY address register (register address 19h). It is
initialized by the five I/O pins designated as PHY[4:0]
during powerup or hardware reset and can be changed
afterward by writing into register address 19h.
MDIO Interrupt.
The LU3X31T-T64 implements inter-
rupt capability that can be used to notify the manage-
ment station of certain events. It generates an active-
high interrupt signal on the MDIOINTZ output pin
whenever one of the interrupt status registers (register
address 1Eh) becomes set while its corresponding
interrupt mask register (register address 1Dh) is
unmasked. Reading the interrupt status register (regis-
ter 1Eh) shows the source of the interrupt and clears
the interrupt output signal.
In addition to the MDIOINTZ pin, the LU3X31T-T64 can
also support the interrupt scheme used by the TI Thun-
derLAN
*
MAC. This option can be enabled by setting
bit 11 of register 17h. Whenever this bit is set, the inter-
rupt is signaled through both the MDIOINTZ pin and
embedded in the MDIO signal.
100Base-X Module
The LU3X31T-T64 implements a 100Base-X compliant
PCS and PMA and 100Base-TX compliant TP-PMD as
illustrated in Figure 3. Bypass options for each of the
major functional blocks within the 100Base-X PCS pro-
vides flexibility for various applications. 100 Mbits/s
PHY loopback is included for diagnostic purposes.
* TIis a registered trademark and ThunderLANis a trademark of
Texas Instruments, Inc.
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| LU3X31T-T64 | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
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