參數(shù)資料
型號: LU3X31T-T64
英文描述: LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX
中文描述: LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州
文件頁數(shù): 27/44頁
文件大小: 580K
代理商: LU3X31T-T64
Lucent Technologies Inc.
27
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers
(continued)
Table 21. PHY Control/Status Register (Register 17h)
Bit(s)
15:14
13
Name
Reserved
CSMODE
Description
R/W
RO
R/W
Default
0h
0h
Reserved.
1
Counter sticks at FFFFh.
0
Counters roll over.
This bit controls the operation of isolate
counter, false carrier counter, and receive
error counters.
1
3-state transmit pairs.
0
Normal operation.
When this bit is set, the twisted-pair trans-
mitter outputs are 3-stated. Note that the
twisted-pair transmit driver can be 3-
stated by either this bit or the TPTXTR pin
(pin 5).
12
TPTXTR
R/W
0h
11
ThunderLANinterrupt Enable 1
MDIO ThunderLANinterrupt enabled.
0
MDIO ThunderLANinterrupt disabled.
This bit enables/disables the TI Thunder-
LAN interrupt mechanism.
MF Preamble Suppression
Enable
0
MDIO preamble suppression disabled.
LU3X31T-T64 can accept management
frames without preamble as described in
bit 6 of register 1h. This bit allows the user
to enable or disable the preamble sup-
pression function.
Speed Status
1
Part is in 100 Mbits/s mode.
0
Part is in 10 Mbits/s mode.
This value is not defined during the auto-
negotiation period.
Duplex Status
1
Part is in full-duplex mode.
0
Part is in half-duplex mode.
This value is not defined during the auto-
negotiation period.
Activity LED On
1
LEDTX/ACTLED active on both trans-
mit and receive.
0
LEDTX/ACTLED active on transmit
only.
LEDRX Off
1
3-state LEDRX output.
0
Normal operation.
LEDTX/ACTLED Off
1
3-state LEDTX/ACTLED output.
0
Normal operation.
LNKLED Off
1
3-state LNKLED output.
0
Normal operation.
LEDCOL Off
1
3-state LEDCOL output.
0
Normal operation.
LEDFD Off
1
3-state LEDFD output.
0
Normal operation.
LEDSP Off
1
3-state LEDSP output.
0
Normal operation.
R/W
0h
10
1
MDIO preamble suppression enabled.
R/W
0h
9
RO
0h
8
RO
0h
7
R/W
0h
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
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