參數(shù)資料
型號(hào)： LU3X31T-T64
英文描述： LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX
中文描述： LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州
文件頁(yè)數(shù)： 14/44頁(yè)
文件大?。?/td> 580K
代理商： LU3X31T-T64
14
Lucent Technologies Inc.
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description
(continued)
Scrambler.
For 100Base-TX applications, the scram-
bler is required to control the radiated emissions at the
media connector and on the twisted-pair cable.
The LU3X31T-T64 implements a data scrambler as
defined by the TP-PMD stream cipher function. The
scrambler uses an 11-bit ciphering linear feedback shift
register (LFSR) with the following recursive linear func-
tion:
X[n] = X[n – 11] + X[n – 9] (modulo 2)
The output of the LFSR is combined with the 5B data
from the symbol encoder via an exclusive-OR logic
function. By scrambling the data, the total energy
launched onto the cable is randomly distributed over a
wide frequency range.
A seed value for the scrambler function can be loaded
by setting bit 4 of register 18h. When this bit is set, the
content of bits 10 though 0 of register 19h, which con-
sists of the 5-bit PHY address and a 6-bit user seed,
will be loaded into the LFSR. By specifying unique
seed value for each PHY in a system, the total EMI
energy produced by a repeater application can be
reduced.
Parallel-to-Serial & NRZ-to-NRZI Conversion.
After
the transmit data stream is scrambled, the 5-bit code-
group is loaded into a shift register and clocked out with
a 125 MHz clock into a serial bit stream. The serialized
data is further converted from NRZ to NRZI format,
which produces a transition on every logic 1 and no
transition on logic 0.
Collision Detect.
During 100 Mbits/s half-duplex oper-
ation, a collision condition is indicated if the transmitter
and receiver become active simultaneously. A collision
condition is indicated by the COL pin (pin 39). For full-
duplex applications, the COL signal is never asserted.
A collision test register exists at address 0, bit 7.
100Base-X Receiver
The 100Base-X receiver consists of functional blocks
required to recover and condition the 125 Mbits/s
receive data stream. The LU3X31T-T64 implements
the 100Base-X receive state machine diagram as given
in ANSIIEEEStandard 802.3u, Clause 24. The
125 Mbits/s receive data stream originates from in a
100Base-TX application.
The receiver block consists of the following functional
blocks:
I
Clock recovery module
I
NRZI/NRZ and serial/parallel decoder
I
Descrambler
I
Symbol alignment block
I
Symbol decoder
I
Collision detect block
I
Carrier sense block
I
Stream decoder block
Clock Recovery.
The clock recovery module accepts
125 Mbits/s scrambled NRZI data stream from either
the on-chip 100Base-TX receiver or from an external
100Base-FX transceiver. The LU3X31T-T64 uses an
onboard digital phase-locked loop (PLL) to extract clock
information of the incoming NRZI data, which is then
used to retime the data stream and set data bound-
aries.
After power-on or reset, the PLL locks to a free-running
25 MHz clock derived from the external clock source.
When initial lock is achieved, the PLL switches to lock
to the data stream, extracts a 125 MHz clock from the
data, and uses it for bit framing of the recovered data.
NRZI-to-NRZ & Serial-to-Parallel Conversion.
The
recovered data is converted from NRZI to NRZ and
then to a 5-bit parallel format for the LU3X31T-T64
descrambler. The 5-bit parallel data is not necessarily
aligned to 4B/5B code-group’s boundary.
Data Descrambling.
The scrambled data is presented
in groups of 5 bits (quints) to a deciphering circuit that
reverses the data scrambling process performed by the
transmitter. The descrambler acquires synchronization
with the data stream by recognizing IDLE bursts of 40
or more bits and locking its deciphering linear feedback
shift register (LFSR) to the state of the scrambling
LFSR. Upon achieving synchronization, the incoming
data is XORed by the deciphering LFSR and descram-
bled, again in groups of 5 bits (quints).
In order to maintain synchronization, the descrambler
continuously monitors the validity of the unscrambled
data that it generates. To ensure this, a link state moni-
tor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the
descrambler, the hold timer starts a 722
μ
s countdown.
相關(guān)PDF資料
PDF描述
LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
LU59002 Consumer IC
LU6612 LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX
LU6612-T64-DB LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX
LU6612 Single-FET for 10Base-T/100Base-TX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX 的單快速以太網(wǎng)收發(fā)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LU3X34FTR 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX
LU3X34FTR-HS128-DB 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX
LU3X54FT 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX
LU3X54FTL 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX
LU3X54FTLHS208 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*