- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367612 > LU3X31T-T64 LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX PDF資料下載
參數(shù)資料
| 型號： | LU3X31T-T64 |
| 英文描述： | LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| 中文描述： | LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州 |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Lucent Technologies Inc.
21
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers
Legend:
RO
R/W
SC
LL
LH
COR
Read only.
Read and write capable.
Self-clearing.
Latching low, unlatch on read.
Latching high, unlatch on read.
Clear on read.
Table 13. Control Register (Register 0h)
Bit(s)
15
Name
Reset
Description
R/W
R/W
SC
Default
0h
1
PHY Reset.
0
Normal operation.
Setting this bit initiates the software reset
function that resets the entire LU3X31T-T64
device, except for the phase-locked loop cir-
cuit. It will relatch in all hardware configura-
tion pin values and set all registers to their
default values. The software reset process
takes 25
μ
s to complete. This bit, which is
self-clearing, returns a value of 1 until the
reset process is complete.
1
Enable loopback mode.
0
Disable loopback mode.
This bit controls the PHY loopback operation
that isolates the network transmitter outputs
(TPTX
±
) and routes the MII transmit data to
the MII receive data path. This function
should only be used when autonegotiation is
disabled (bit 12 = 0). The specific PHY
(10Base-T or 100Base-X) used for this oper-
ation is determined by bits 12 and 13 of this
register.
1
100 Mbits/s.
0
10 Mbits/s.
Link speed is selected by this bit or by auto-
negotiation if bit 12 of this register is set (in
which case, the value of this bit is ignored).
At powerup or reset, this bit will be set unless
AUTONEN, 100FDEN, and 100HDEN pin
are all in logic low state.
1
Enable autonegotiation process.
0
Disable autonegotiation process.
This bit determines whether the link speed
should be set up by the autonegotiation pro-
cess. It is set at powerup or reset if the
AUTONEN pin (pin 4) detects a logic 1 input
level.
14
Loopback
R/W
0h
13
Speed Selection
R/W
Pin
12
Autonegotiation Enable
R/W
Pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X31T-T64 | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| LU59002 | Consumer IC |
| LU6612 | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| LU6612-T64-DB | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| LU6612 | Single-FET for 10Base-T/100Base-TX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX 的單快速以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。