參數(shù)資料
型號(hào): LU3X31T-T64
英文描述: LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX
中文描述: LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州
文件頁(yè)數(shù): 20/44頁(yè)
文件大小: 580K
代理商: LU3X31T-T64
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
20
Lucent Technologies Inc.
Functional Description
(continued)
Table 11. Autonegotiation
100Base-X PCS Configuration
The logic state of BPSCR, BP4B5B, and BPALIGN pins latched into bits 15, 14, and 12 of the Config 100 register at
address 18h during powerup or reset. These registers configure the functionality of 100Base-X PCS (physical cod-
ing sublayer) MII registers.
Table 12. MII Management Registers
Configuration Pins at RESET
Registers Initial Value
AUTOEN
Pin 4
100FDEN
Pin 2
(Reg 4.8)
1
0
0
0
0
X
100HDEN
Pin 11
(Reg 4.7)
X
1
1
0
0
X
10FDEN
Pin 17
(Reg 4.6)
X
1
0
1
0
X
10HDEN
Pin 43
(Reg 4.5)
X
X
X
X
1
X
Autonegotiate
Reg 0.12
Speed
Reg 0.13
Duplex
Reg 0.8
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
Address
0h
1h
2h
3h
4h
5h
6h
7h
Fh
15h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
Register Name
Basic/Extended
B
B
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Control Register
Status Register
PHY Identifier Register
Autonegotiation Advertisement Register
Autonegotiation Link Partner Ability Register
Autonegotiation Expansion Register
IEEE Reserved
Receive Error Counter
PHY Control/Status Register
Config 100 Register
PHY Address Register
Config 10 Register
Status 100 Register
Status 10 Register
Interrupt Mask Register
Interrupt Status Register
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