參數(shù)資料
型號: M12S128168A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 200萬× 16位× 4個銀行同步DRAM
文件頁數(shù): 22/44頁
文件大小: 967K
代理商: M12S128168A
ES MT
8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
M12S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
Nov. 2006
22/44
9. MRS
*Note: 1. t
BDL
: 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
3. Write burst is terminated. t
BDL
determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying t
RAS
min delay) with DQM.
6. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
CLK
C M D
PRE
*Not e 4
M R S
AC T
t
R P
2C LK
1) Mo d e R e g is t e r S e t
CLK
CMD
DQ(CL2)
DQ(CL3)
CLK
CMD
DQM
DQ
D0
D1
D2
D3
W R
STOP
* N o t e 1
Q0
Q1
Q0
Q1
RD
STOP
* No t e2
2 ) R e a d B u r s t S t o p ( B L = 4 )
D5
D4
CLK
CMD
DQ(CL3)
CLK
CMD
DQM
DQ
D0
D1
Mask Mas k
W R
Q0
Q1
RD
PRE
1 ) W r i t e i n t e r r u p t e d b y p r e ch a r g e ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( BL = 4 )
* No t e 2
PRE
* No t e4
*No t e 3
DQ(CL2)
* No t e5
Q2
Q1
Q2
Q3
Q0
t
RD L
t
B D L
Q3
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