參數(shù)資料
型號(hào)： M2S56D30AKT-75
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 32M X 8 DDR DRAM, 0.75 ns, PDSO64
封裝： 0.40 MM PITCH, STSOP-64
文件頁數(shù)： 11/41頁
文件大?。?/td> 638K
代理商： M2S56D30AKT-75
19
DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
M2S56D20/ 30/ 40AKT
-60
-75A / -75
x4
110
95
x8
120
100
x16
140
115
x4
180
140
x8
190
150
x16
220
180
x4
180
130
x8
190
140
x16
220
160
IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN)
ALL
150
140
-60/-75A/-75
3
9
-60/-75A/-75 L
2
9,21
-60/-75AU/-75 UL
1
9,22
x4
270
215
20
x8
290
235
20
x16
330
270
20
IDD2P
IDD2F
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
Notes
IDD0
IDD1
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;
Address and control inputs changing once per clock cycle
Symbol
Organization
Parameter/Test Conditions
OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN;
t CK = t CK MIN; DQ, DM and DQS inputs changing twice per clock
cycle; address and control inputs changing once per clock cycle
Unit
Limits(Max.)
ALL
85
100
35
30
15
20
ALL
45
IDD7
OPERATING CURRENT-Four bank Operation: Four bank are interleaved
with BL=4, refer to the Notes 20
55
IDD4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank
active; Address and control inputs changing once per clock cycle;CL=2.5;
t CK = t CK MIN; IOUT = 0 mA
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE <VIL (MAX); t CK = t CK MIN
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; CKE < VIL (MAX); t CK = t CK MIN
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One
bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM
and DQS inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
IDD3N
IDD6
SELF REFRESH CURRENT: CKE < 0.2V
6
10
ALL
IDD4W
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
CL=2.5; t CK = t CK MIN;DQ, DM and DQS inputs changing twice per
clock cycle
ALL
AVERAGE SUPPLY CURRENT from VDD
(TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, Output Open, unless otherwise noted)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, Output Open, unless otherwise noted)
Min.
Max.
VIH(AC) High-Level Input Voltage (AC)
VREF + 0.31
VIL(AC) Low-Level Input Voltage (AC)
VREF - 0.31
VID(AC) Input Differential Voltage, CLK and /CLK
0.7
VDDQ + 0.6
7
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
0.5*VDDQ - 0.2 0.5*VDDQ + 0.2
8
IOZ
Off-state Output Current /Q floating Vo=0 to VDDQ
-5
5
II
Input Current / VIN=0 to VDDQ
-2
2
IOH
Output High Current (VOUT = VTT+0.84V)
-16.8
IOL
Output High Current (VOUT = VTT-0.84V)
16.8
Symbol
Parameter / Test Conditions
Unit
V
mA
Notes
Limits
V
uA
相關(guān)PDF資料
PDF描述
M2V56S30ATP-6 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2S56D30AKT-75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30AKT-75AL 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30AKT-75L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30ATP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
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