參數(shù)資料
型號(hào): M2S56D30AKT-75
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 32M X 8 DDR DRAM, 0.75 ns, PDSO64
封裝: 0.40 MM PITCH, STSOP-64
文件頁(yè)數(shù): 14/41頁(yè)
文件大?。?/td> 638K
代理商: M2S56D30AKT-75
21
DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
M2S56D20/ 30/ 40AKT
AC TIMING REQUIREMENTS (2/2)
(TA=0 to 70oC, VDD = VDDQ = 2.5V +0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Min.
Max
Min.
Max
Min.
Max
tRAS
Row Active time
42
120,000
45
120,000
45
120,000
ns
tRC
Row Cycle time(operation)
60
65
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
72
75
ns
tRCD
Row to Column Delay
18
20
ns
tRP
Row Precharge time
18
20
ns
tRRD
Act to Act Delay time
12
15
ns
tWR
Write Recovery time
15
ns
tDAL
Auto Precharge write recovery + precharge time
35
ns
tWTR Internal Write to Read Command Delay
1
tCK
tXSNR Exit Self Ref. to non-Read command
75
ns
tXSRD Exit Self Ref. to -Read command
200
tCK
tXPNR Exit Power down to command
1
tCK
tXPRD Exit Power down to -Read command
1
tCK
18
tREFI Average Periodic Refresh interval
7.8
us
17
Unit
Notes
Symbol
AC Characteristics Parameter
-75A
-75
-60
Output Load Condition
DQ
Output Timing
Measurement
Reference Point
VREF
DQS
VOUT
VREF
30pF
50
VTT=VREF
Zo=50
CAPACITANCE
(TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Min. Max.
CI(A)
Input Capacitance, address pin
VI=1.25v
2.0
3.0
pF
11
CI(C)
Input Capacitance, control pin
f=100MHz
2.0
3.0
pF
11
CI(K)
Input Capacitance, CLK pin
VI=25mVrms 2.0
3.0
0.25
pF
11
CI/O
I/O Capacitance, I/O, DQS, DM pin
4.0
5.0
0.50
pF
11
0.50
Notes
Limits
Symbol
Parameter
Test Condition
Unit
Delta
Cap.(Max.)
相關(guān)PDF資料
PDF描述
M2V56S30ATP-6 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
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