deveopmen
Serial I/O
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
120
Serial I/O
Serial I/O is configured as five channels: UART0 to UART4.
UART0 to 4
UART0 to UART4 each have an exclusive timer to generate a transfer clock, so they operate independently
of each other.
Figure 1.16.1 and 1.16.2 show the block diagram of UARTi (i=0 to 4). Figures 1.16.3 and 1.16.4 show the
block diagram of the transmit/receive unit.
UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O
mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 0360
16
,
0368
16
, 0338
16
, 0328
16
and 02F8
16
) determine whether UARTi is used as a clock synchronous serial I/O or
as a UART. Although a few functions are different, UART0 to UART4 have almost the same functions.
UART2 to UART4, in particular, are compliant with the SIM interface with some extra settings added in
clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates
an interrupt request if the TxD pin and the RxD pin are different in level.
Table 1.16.1 shows the comparison of functions of UART0 to UART4, and Figures 1.16.5 through 1.16.11
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
UART0
UART1
UART2
Function
CLK polarity selection
Continuous receive mode
selection
LSB first / MSB first selection
Impossible
Transfer clock output from
multiple pins selection
Impossible
Impossible
Impossible
Impossible
Serial data logic switch
Impossible
Sleep mode selection
Impossible
Impossible
TxD, RxD I/O polarity switch
Impossible
Possible
CMOS output
TxD, RxD port output format
CMOS output
N-channel open
drain output
Impossible
Parity error signal output
Impossible
Impossible
Bus collision detection
Impossible
Possible
Possible
(Note 1)
Separate CTS/RTS pins
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 3)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 3)
Possible
Possible
(Note 1)
Possible
(Note 2)
Possible
(Note 1)
Possible
(Note 4)
Possible
(Note 4)
UART3
Impossible
Impossible
Impossible
Possible
Possible
Possible
(Note 1)
Possible
(Note 2)
Possible
(Note 1)
Possible
(Note 4)
Possible
(Note 4)
UART4
Impossible
Impossible
Impossible
Possible
Possible
Possible
(Note 1)
Possible
(Note 2)
Possible
(Note 1)
Possible
(Note 4)
Possible
(Note 4)
CMOS output
CMOS output
Table 1.16.1. Comparison of functions of UART0 to UART4