
deveopmen
Timing (Vcc = 3V)
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
240
V
CC
= 3V
Switching characteristics (referenced to V
CC
= 3V, V
SS
= 0V at Topr = 25
o
C, CM15 = “1” unless
otherwise specified)
Table 1.28.41. Memory expansion and microprocessor modes
(with wait, accessing external memory, multiplex bus area selected)
Symbol
Standard
Min.
Measuring condition
Max.
25
Parameter
Unit
t
d(BCLK-AD)
t
h(BCLK-AD)
t
h(RD-AD)
t
h(WR-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
ns
ns
ns
ns
0
t
h(BCLK-CS)
t
h(RD-CS)
t
h(WR-CS)
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
0
ns
ns
ns
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-ALE)
t
h(ALE-AD)
t
dz(RD-AD)
t
h(BCLK-DB)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
Address output flowting start time
DB signal output hold time (BCLK standard)
25
ns
ns
ns
ns
ns
ns
– 2
(Note)
t
d(BCLK-RD)
t
h(BCLK-RD)
t
d(BCLK-WR)
t
h(BCLK-WR)
t
d(DB-WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
25
ns
ns
ns
ns
ns
0
25
0
t
h(WR-DB)
Data output hold time (WR standard)
(Note)
ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
t
d(DB – WR)
=
10 X m
f
(BCLK)
X 2
– 40
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
t
d(BCLK-CS)
Chip select output delay time
25
ns
(Note)
(Note)
(Note)
t
h(RD – AD)
=
f
(BCLK)
X 2
10
9
10
9
– 20
[ns]
t
h(WR – AD)
=
f
(BCLK)
X 2
10
9
– 20
[ns]
t
h(RD – CS)
=
f
(BCLK)
X 2
10
9
– 20
[ns]
(Note)
(Note)
8
t
h(WR – CS)
=
f
(BCLK)
X 2
– 20
[ns]
t
h(WR – DB)
=
f
(BCLK)
X 2
10
9
– 20
[ns]
t
d(AD – ALE)
=
f
(BCLK)
X 2
10
9
– 27
[ns]
t
h(ALE – AD)
=
f
(BCLK)
X 2
10
9
– 20
[ns]
0
Figure 1.28.1