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UARTi Special Mode Register
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
160
Master SS input
Data output timing
Data input timing
D
0
D
1
D
2
D
3
D
4
D
6
D
7
D
5
"H"
"L"
Clock output
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
"H"
"L"
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
"H"
"L"
Clock Phase Setting
With bit 1 of UARTi special mode register 3 (addresses 0325
16
and 02F5
16
[i = 3 or 4]) and bit 6 of
UARTi transmission-reception control register 0 (addresses 032C
16
and 02FC
16
[i = 3 or 4]), four
combinations of transfer clock phase and polarity can be selected.
Bit 6 of UARTi transmission-reception control register 0 (addresses 032C
16
and 02FC
16
[i = 3 or 4])
sets transfer clock polarity, whereas bit 1 of UARTi special mode register 3 (addresses 0325
16
and
02F5
16
[i = 3 or 4]) sets transfer clock phase.
Transfer clock phase and polarity must be the same between the master and slave involved in the
transfer.
< Master (Internal Clock) (DINC = 0) >
Figure 1.20.7 shows the transmission and reception timing.
< Slave (External Clock) (DINC = 1) >
With “0” for bit 1 (CKPH) of UARTi special mode register 3 (addresses 0325
16
and 02F5
16
[i = 3 or
4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level,
the serial transmission start condition is satisfied, though output is indeterminate. After that, serial
transmission is synchronized with the clock. Figure 1.20.8 shows the timing.
With “1” for bit 1 (CKPH) of UARTi special mode register 3 (addresses 0325
16
and 02F5
16
[i = 3 or
4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level,
the first data is output. After that, serial transmission is synchronized with the clock. Figure 1.20.9
shows the timing.
Figure 1.20.7. The transmission and reception timing in master mode (internal clock)