deveopmen
DRAM Controller
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
179
DRAM Controller
There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of
DRAM. Table 1.25.1 shows the functions of the DRAM controller.
Table 1.25.1
DRAM space
Bus control
Refresh
DRAM Controller Functions
512KB, 1MB, 2MB, 4MB, 8MB
2CAS/1W
________
Self refresh-compatible
Function modes
EDO-compatible, fast page mode-compatible
Waits
1 wait or 2 waits, programmable
________
To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 0040
16
)
to specify the DRAM size. Figure 1.25.1 shows the DRAM control register.
The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 0005
16
are “11
2
”).
Always use the DRAM controller in external memory modes 0, 1, or 2.
When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 0004
16
).
Set wait time between after DRAM power ON and before memory processing, and dummy cycle for reflesh
by sowtwear.
DRAM control register
Symbol
Address
00040
16
When reset
Indeterminate (Note 4)
DRAMCONT
Bit name
Function
Bit symbol
W
R
b7 b6 b5 b4 b3
b2 b1 b0
AR1
WT
AR0
AR2
0 0 1 : Inhibit
0 1 0 : 0.5MB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Inhibit
b3 b2 b1
DRAM space select bit
Wait select bit (Note 1)
Self-refresh mode bit
(Note 2)
SREF
0 : Two wait
1 : One wait
0: Self-refresh OFF
1: Self-refresh ON
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
Note 1: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1.
Note 2: When you set "1", both RAS and CAS change to "L". When you set "0",
RAS and CAS change to "H" and then normal operation (read/write, refresh)
is resumed. In Stop mode, there is no control.
Note 3: Set the bus width using the external data bus width control register (address
0005
16
). When selecting 8-bit bus width, CASH is indeterminate.
Note 4: After reset, the content of this register is indeterminate.
DRAM controller begins executing after writing to this register.
Figure 1.25.1. DRAM control register