deveopmen
CPU Rewrite Mode (Flash Memory Version)
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
260
Flash memory control register 0
Symbol
FMR0
Address
0377
16
When reset
XX000001
2
R
b7
b6
b5
b4
0
b3
b2 b1
b0
FMR00
Bit symbol
Bit name
Function
RW
0: Busy (being written or erased)
1: Ready
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMR01
0: Boot ROM area is accessed
1: User ROM area is accessed
Lock bit disable bit
(Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
Flash memory reset bit
(Note 3)
0: Normal operation
1: Reset
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
User ROM area select bit (
Note 4) (Effective in only
boot mode)
FMR02
FMR03
FMR05
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to this bit.
AA
A
AA
AA
AA
AA
AA
AA
AA
RY/BY status flag
Flash memory control register 1
b7
b6
b5 b4
b3
b2
Symbol
FMR1
Address
0376
16
When reset
XXXX0XXX
2
R
RW
A
b1
b0
Bit symbol
Bit name
Function
Flash memory power
supply-OFF bit (Note)
0: Flash memory power supply is
connected
1: Flash memory power supply-off
FMR13
0
Note : For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit.
During parallel I/O mode,programming,erase or read of flash memory is not controlled by
this bit,only by external pins.
A
A
A
A
0
0
0
0
0
Reserved bit
Must always be set to “0”
A
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
0
Figure 1.30.1. Flash memory control registers
Figure 1.30.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.30.3 shows a flow-
chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.