deveopmen
Processor Mode
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
25
Figure 1.6.1. Processor mode register 0
Processor mode register 0 (Note 1)
Symbol
PM0
Address
0004
16
When reset
80
16
(Note 2)
Bit name
Function
Bit symbol
b7
b6
0
b5
b4
b3
b2
b1
b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
b1 b0
PM03
PM01
PM00
Processor mode bit
PM02
R/W mode select bit
(Note 7)
Software reset bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
The device is reset when this bit is set to “1”.
The value of this bit is “0” when read.
PM04
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
b5 b4
Multiplexed bus space
select bit (Note 3)
PM05
PM07
BCLK output disable bit
(Note 5)
0 : BCLK is output (Note 6)
1 : Function set by bit 0,1 of system
clock control register 0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values to this register.
Note 2: If the V
CC
voltage is applied to the CNV
SS
, the value of this register when reset is 03
16
. (PM00 is set
to “1” and PM07 is set to “0”.)
Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when
mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a
result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in
microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and
bit 1 (CM01) of system clock control register 0 (address 0006
16
) = "0". "L" is now output from P5
3
.
Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 7: When using 16-bit bus width in DRAM controler, set this bit to "1".
W
R
AA
AA
AA
AA
AA
Reserved bit
Must always be set to “0”