deveopmen
Clock Generating Circuit
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
45
Table 1.8.2. Clock output setting (single chip mode)
PM07
0/1
CM01
0
CM00
0
PM14
Ignored
P5
3
/BCLK/ALE/CLK
OUT
pin function
1
1
1
0
1
1
Ignored
Ignored
Ignored
Ignored
Ignored
Ignored
Ignored
PM15
P5
3
I/O port
fc output
f
8
output
f
32
output
BCLK output function
select bit
Clock output function select
bit
ALE pin select bit
1
0
1
Note :Must use P5
7
as input port.
(Note)
(Note)
(Note)
Table 1.8.3. Clock output setting (memory expansion/microprocessor mode)
BCLK output function
select bit
bit
0
1
1
1
0
0
0
1
1
1
0
1
0
0
BCLK output
"L" output (not P5
3
)
fc output
f
8
output
0
0
1
0
1
1
0
0
1
f
32
output
ALE output
1
0
PM07
CM01
CM00
PM14
P5
3
/BCLK/ALE/CLK
OUT
pin function
Ignored
PM15
Clock output function select
ALE pin select bit
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 0007
16
) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V
CC
re-
mains above 2V.
Because the oscillation of BCLK, f
1
to f
32
, f
1SIO2
to f
32SIO2
, fc, fc
32
, and f
AD
stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.8.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt.
When using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a
priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009F
16
) for
exiting a stop/wait state. Set the interrupt priority set bits for the exit from a stop/wait state to the same level
as the flag register (FLG) processor interrupt level (IPL). Figure 1.8.6 shows the exit priority register.
When exiting stop mode using an interrupt, the relevant interrupt routine is executed.
When shifting to stop mode and reset, the main clock division register (000C
16
) is set to “08
16
”.