Clock asynchronous serial I/O (UART) mode
deveopmen
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
148
Figure 1.19.1. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
Start
bit
Parity
bit
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”.
“0”
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
Data is set in UARTi transmit buffer register
SP
A “L” level returns from SIM card due
to the occurrence of a parity error.
The level is detected by the
interrupt routine.
The level is detected by
the interrupt routine.
Receive enable
bit (RE)
Receive complete
flag (RI)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
Start
bit
Parity
bit
TxD
i
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “0”.
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
Receive interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
SP
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
A “L” level returns from TxD
2
due to
the occurrence of a parity error.
RxD
i
Read to receive buffer
Read to receive buffer
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
Signal conductor level
(Note 1)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
SP
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
SP
SP
TxD
i
RxD
i
Signal conductor level
(Note 1)
Note: Equal in waveform because TxD
i
and RxD
i
are connected.
Transferred from UARTi transmit buffer register to UARTi transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: After writing to the transfer buffer at above timing, transmission starts at the timing of BRG overflow.
(Note)