參數(shù)資料
型號: M58WR064KU70ZA6U
廠商: NUMONYX
元件分類: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝: 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù): 43/122頁
文件大小: 2187K
代理商: M58WR064KU70ZA6U
M58WRxxxKU, M58WRxxxKL
Command interface - standard commands
5.10
Protection Register Program command
The Protection Register Program command programs the 128 bit user one-time-
programmable (OTP) segment of the protection register and the protection register lock.
The segment is programmed 16 bits at a time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
The first bus cycle sets up the Protection Register Program command.
The second latches the address and the data to be written to the protection register
and starts the program/erase controller.
Read operations output the status register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register
(Figure 6: Protection register memory map). Attempting to program a previously protected
protection register results in a status register error. The protection of the protection register
is not reversible.
The protection register program cannot be suspended. Dual operations between the
parameter bank and the protection register memory space are not allowed (see Table 16:
flowchart for using the Protection Register Program command.
5.11
Set Configuration Register command
The Set Configuration Register command writes a new value to the configuration register
which defines the burst length, type, X latency, synchronous/asynchronous read mode, and
the valid Clock edge configuration.
Two bus write cycles are required to issue the Set Configuration Register command.
The first cycle writes the setup command and the address corresponding to the
configuration register content.
The second cycle writes the configuration register data and the confirm command.
Once the command is issued the memory returns to read mode.
The values of the configuration register must always be presented on ADQ15-ADQ0. CR0 is
on ADQ0, CR1 on ADQ1, and so on. The other address bits are ignored.
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