![](http://datasheet.mmic.net.cn/190000/M58WR064KU70ZA6U_datasheet_14929077/M58WR064KU70ZA6U_38.png)
Status register
M58WRxxxKU, M58WRxxxKL
7
Status register
The status register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the status
the contents the status register is latched and updated on the falling edge of the Chip
Enable or Output Enable signals and can be read until Chip Enable or Output Enable
returns to VIH. The status register can only be read using single asynchronous or single
synchronous reads. Bus read operations from any address within the bank, always read the
status register during program and erase operations.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 provide information on the status of the device and are set and
reset by the device. Bits SR5, SR4, SR3 and SR1 provide information on errors; they are set
by the device but must be reset by issuing a Clear Status Register command or a hardware
reset. If an error bit is set to ‘1’ the status register should be reset before issuing another
command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the
addressed bank.
Table 10 in conjunction with the following sections.
7.1
Program/erase controller status bit (SR7)
The program/erase controller status bit indicates whether the program/erase controller is
active or inactive in any bank. When the program/erase controller status bit is Low (set to
‘0’), the program/erase controller is active; when the bit is High (set to ‘1’) the program/erase
controller is inactive and the device is ready to process a new command.
The program/erase controller status bit is Low immediately after a Program/Erase Suspend
command is issued until the program/erase controller pauses. After the program/erase
controller pauses the bit is High.
During program and erase operations the program/erase controller status bit can be polled
to find the end of the operation. Other bits in the status register should not be tested until the
program/erase controller completes the operation and the bit is High.
After the program/erase controller completes its operation the erase status, program status,
VPP status and block lock status bits should be tested for errors.
7.2
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended or is
going to be suspended in the addressed block. When the erase suspend status bit is High
(set to ‘1’), a Program/Erase Suspend command has been issued and the memory is
waiting for a Program/Erase Resume command.
The erase suspend status should only be considered valid when the program/erase
controller status bit is High (program/erase controller inactive). SR7 is set within the erase
suspend latency time of the Program/Erase Suspend command being issued; therefore, the
memory may still complete the operation rather than entering suspend mode.
When a Program/Erase Resume command is issued the erase suspend status bit returns
Low.