參數(shù)資料
型號: M58WR064KU70ZA6U
廠商: NUMONYX
元件分類: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝: 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù): 6/122頁
文件大?。?/td> 2187K
代理商: M58WR064KU70ZA6U
M58WRxxxKU, M58WRxxxKL
Common flash interface
(P+36)h = 6Fh
07h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
(P+37)h = 70h
00h
(P+38)h = 71h
20h
(P+39)h = 72h
00h
(P+3A)h = 73h
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+3B)h = 74h
00h
(P+3C)h = 75h
01h
Bank Region 2 (Erase Block Type 2): bits per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+3D)h = 76h
03h
Bank Region 2 (Erase Block Type 2): Page mode and
synchronous mode capabilities (defined in Table 43)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+3E)h = 77h
Feature space definitions
(P+3F)h = 78h
Reserved
1.
The variable P is a pointer that is defined at CFI offset 15h.
2.
Applies to M58WR016KL.
3.
Applies to M58WR032KL.
4.
Applies to M58WR064KL.
5.
Bank regions. There are two bank regions - see Tables 31, 32, 33, 34, 35 and 36.
Table 46.
Bank and erase block region 2 information(1) (continued)
M58WR016KU,
M58WR032KU,
M58WR064KU
M58WR016KL,
M58WR032KL,
M58WR064KL
Description
Offset
Data
Offset
Data
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