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參數(shù)資料
| 型號(hào)： | M58WR064KU70ZA6U |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁(yè)數(shù)： | 51/122頁(yè) |
| 文件大小： | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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Command interface - factory program commands
M58WRxxxKU, M58WRxxxKL
6.3.2
Program phase
The program phase requires n+1 cycles, where n is the number of words (refer to Table 9:
Three successive steps are required to issue and execute the program phase of the
command.
1.
Use one bus write operation to latch the start address and the first word to be
programmed. The status register bank write status bit SR0 should be read to check
that the P/EC is ready for the next word.
2.
Each subsequent word to be programmed is latched with a new bus write operation.
The address can either remain the start address, in which case the P/EC increments
the address location, or the address can be incremented, in which case the P/EC
jumps to the new address. If any address that is not in the same block as the start
address is given with data FFFFh, the program phase terminates and the verify phase
begins. The status register bit SR0 should be read between each bus write cycle to
check that the P/EC is ready for the next word.
3.
Finally, after all words have been programmed, write one bus write operation with data
FFFFh to any address outside the block containing the start address, to terminate the
programming phase.
The memory is now set to enter the verify phase.
6.3.3
Verify phase
The verify phase is similar to the program phase in that all words must be resent to the
memory for them to be checked against the programmed data. The program/erase
controller checks the stream of data with the data that was programmed in the program
phase and reprograms the memory location if necessary.
Three successive steps are required to execute the verify phase of the command.
1.
Use one bus write operation to latch the start address and the first word, to be verified.
The status register bit SR0 should be read to check that the program/erase controller is
ready for the next word.
2.
Each subsequent word to be verified is latched with a new bus write operation. The
words must be written in the same order as in the program phase. The address can
remain the start address or be incremented. If any address that is not in the same block
as the start address is given with data FFFFh, the verify phase terminates. status
register bit SR0 should be read to check that the P/EC is ready for the next word.
3.
Finally, after all words have been verified, write one bus write operation with data
FFFFh to any address outside the block containing the start address, to terminate the
verify phase.
If the verify phase is successfully completed the memory remains in read status register
mode. If the program/erase controller fails to reprogram a given location, the error is
signaled in the status register.
6.3.4
Exit phase
When the status register P/EC bit SR7 is set to ‘1’ this indicates that the device has returned
to read mode. A full status register check should be done to ensure that the block has been
successfully programmed. See Section 7: Status register for more details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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