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參數(shù)資料
| 型號(hào)： | M58WR064KU70ZA6U |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁(yè)數(shù)： | 62/122頁(yè) |
| 文件大?。?/td> | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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Configuration register
M58WRxxxKU, M58WRxxxKL
8.9
Power-down bit (CR5)
The power-down bit is enables or disables the power-down function. When it is set to ‘0’ the
power-down function is disabled. If the Reset/Power-down, RP, pin goes Low (VIL), the
device is reset and the supply current IDD is reduced to the standby value IDD3. When the
power-down bit is set to ‘1’ the power-down function is enabled. If the Reset/Power-down,
RP, pin goes Low (V
IL) the device switches to the power-down state and the supply current
IDD is reduced to the reset/power-down value, IDD2.
The recovery time after a reset/power-down, RP, pulse is significantly longer when power-
down is enabled (see Table 28: Reset and power-up AC characteristics).
8.10
Wrap burst bit (CR3)
The burst reads can be confined inside the 4-, 8- or 16-word boundary (wrap) or overcome
the boundary (no wrap). The wrap burst bit selects wrap and no wrap. When the wrap burst
bit is set to ‘0’ the burst read wraps, and when it is set to ‘1’ the burst read does not wrap.
8.11
Burst length bits (CR2-CR0)
The burst length bits set the number of words to be output during a synchronous burst read
operation as result of a single address latch cycle. They can be set for 4 words, 8 words,
16 words or continuous burst, where all the words are read sequentially.
In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode or in 4-, 8-, 16-word no-wrap, depending on the starting address,
the device asserts the WAIT output to indicate that a delay is necessary before the data is
output.
If the starting address is aligned to a 4-word boundary no wait states are needed and the
WAIT output is not asserted.
If the starting address is shifted by 1, 2, or 3 positions from the 4-word boundary, WAIT is
asserted for 1, 2, or 3 clock cycles when the burst sequence crosses the first 16-word
boundary to indicate that the device needs an internal delay to read the successive words in
the array. WAIT is only asserted once during a continuous burst access. See also Table 13:
CR4 is reserved for future use.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5L28FGNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L14FCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L15TGNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M5L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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