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參數(shù)資料
| 型號： | MAX3108EWA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/56頁 |
| 文件大小： | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
23
Maxim Integrated
Transmitter Flow Control
If auto transmit control is enabled by the FlowCtrl[5:4]
bits, the receiver compares all received words with the
XOFF and XON characters. When an XOFF character
is received, the MAX3108 halts the transmitter from
sending further data following any currently transmitting
word. The receiver is not affected and continues receiv-
ing. Upon receiving an XON character, the transmitter
restarts sending data. The received XON and XOFF
characters are filtered out and are not stored into the
receive FIFO. An interrupt is not generated.
If double-wide (16-bit) XON/XOFF characters are select-
ed by setting the FlowCtrl[5:4] bits to 11, then a char-
acter matching XON1/XOFF1 must be received before
a character matching XON2/XOFF2 in order to be inter-
preted as a control character.
Turn the transmitter off by setting the MODE1[1]: TxDisabl
bit high before enabling software transmitter flow control.
FIFO Interrupt Triggering
Receive and transmit FIFO fill-dependent interrupts are
generated if FIFO trigger levels are defined. When the
number of words in the FIFOs reach or exceed a trig-
ger level programmed in the FIFOTrgLvl register, an
interrupt is generated in ISR[3] or ISR[4]. The interrupt
trigger levels operate independently from the HALT and
RESUME flow control levels in AutoRTS or auto software
flow control modes.
The FIFO interrupt triggering can be used, for example,
for a block data transfer. The trigger level interrupt gives
the host an indication that a given block size of data is
available for reading in the receive FIFO or available for
transfer to the transmit FIFO. If the HALT and RESUME
levels are outside of this range, then the UART continues
to transmit or receive data during the block read/write
operations for uninterrupted data transmission on the bus.
Low-Power Standby Modes
The MAX3108 has sleep and shutdown modes that
reduce power consumption during periods of inactivity.
In both sleep and shutdown modes, the UART disables
specific functional blocks to reduce power consumption.
After sleep or shutdown mode is exited, the internal clock
starts up and a period of time is needed for clock stabi-
lization. The STSInt[5]: ClkReady bit indicates when the
clocks are stable. When an external clock source is used,
the ClkReady bit does not indicate clock stability.
Forced-Sleep Mode
In forced-sleep mode, all UART-related on-chip clock-
ing is stopped. The following blocks are inactive: the
crystal oscillator, the PLL, the predivider, the receiver,
and the transmitter. The I2C/SPI interface and the reg-
isters remain active and the host controller can access
them. To force the MAX3108 to enter sleep mode, set the
MODE1[5]: ForcedSleep bit high. To exit forced-sleep
mode, set the ForcedSleep bit low.
Auto-Sleep Mode
The MAX3108 can be configured to operate in auto-sleep
mode by setting the MODE1[6]: AutoSleep bit high. In
auto-sleep mode, the MAX3108 automatically enters
sleep mode when all the following conditions are met:
BothFIFOsareempty.
TherearenopendingIRQ interrupts.
There is no activity on any input pins for a period
equal to 65,536 UART character lengths.
The same blocks are inactive when the UART is in auto-
sleep mode as in forced-sleep mode.
The MAX3108 exits auto-sleep mode as soon as activity
is detected on any of the GPIO_, RX, or CTS inputs.
To manually exit auto-sleep mode, set the MODE1[6]:
AutoSleep bit low.
Shutdown Mode
Drive the RST input to logic-low to enter shutdown mode.
Shutdown mode consumes the least possible amount
of power. In shutdown mode, all the MAX3108 circuitry
is off except for the 1.8V LDO. This includes the I2C/
SPI interface, the registers, the FIFOs, and the clocking
circuitry.
When the RST input transitions from low to high, the
MAX3108 exits shutdown mode and a hardware reset is
initiated The chip initialization is complete when the IRQ
output is logic high.
The MAX3108 needs to be reprogrammed following a
shutdown.
Power-Up and IRQ
The IRQ output has two functions. During normal opera-
tion (the MODE1{7}. IRQSel bit is 1), IRQ operates a
hardware active-low interrupt output; IRQ is asserted
when an interrupt is pending. An IRQ interrupt is only
possible during normal operation if at least one of the
interrupt enable bits in the IRQEn register is set.
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| MAX3109ETJ+ | 功能描述:UART 接口集成電路 Dual Serial UART with 128-Word FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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| MAX310C/D | 功能描述:多路器開關(guān) IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關(guān)閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
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