SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 39 Maxim Integrated IrDA Registe" />
參數(shù)資料
型號(hào)： MAX3108EWA+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 33/56頁(yè)
文件大?。?/td> 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
39
Maxim Integrated
IrDA Register
The IrDA register allows selection of IrDA SIR- and MIR-compliant pulse shaping at the TX and RX interfaces. It also
allows inversion of the TX and RX logic, separate from whether IrDA pulse shaping is enabled or not.
Bits 7, 6, and 2: No Function
Bit 5: TxInv
Set the TxInv bit high to invert the logic at the TX output. This functionality is separate from IrDA operation.
Bit 4: RxInv
Set the RxInv bit high to invert the logic at the RX input. This functionality is separate from IrDA operation.
Bit 3: MIR
Set the MIR and IrDAEn bits high to select IrDA 1.1 (MIR) with 1/4-period pulse widths.
Bit 1: SIR
Set the SIR and IrDAEn bits high to select IrDA 1.0 pulses (SIR) with 3/16th-period pulse widths.
Bit 0: IrDAEn
Set the IrDAEn bit high to program the MAX3108 to produce IrDA-compliant pulses at the TX output and expect IrDA-
compliant pulses at the RX input. If IrDAEn is set low, normal (non-IrDA) pulses are generated by the transmitter and
expected by the receiver. Use IrDAEn in conjunction with the SIR or MIR bits to select the pulse width.
Flow Level Register (FlowLvl)
The FlowLvl register is used for selecting the RxFIFO threshold levels used for auto software (XON/XOFF) and hard-
ware (RTS/CTS) flow control.
Bits 7–4: Resumex
The Resumex bits set the receive FIFO threshold at which an XON character is automatically sent in auto software flow
control mode or RTS is automatically asserted in AutoRTS mode. These flow control actions occur once the RxFIFO is
emptied to below the value in Resumex. This signals the far-end station to resume transmission. The threshold level is
calculated as 8 x Resumex. The resulting possible threshold-level range is 0 to 120 (decimal).
Bits 3–0: Haltx
The Haltx bits set the receive FIFO threshold level at which an XOFF character is automatically sent in auto software
flow control mode or RTS is automatically deasserted in AutoRTS mode. These flow control actions occur once the
RxFIFO is filled to above the value in Haltx. This signals the far-end station to halt transmission. The threshold level is
calculated as 8 x Haltx. The resulting possible threshold-level range is 0 to 120 (decimal).
ADDRESS:
0x0E
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
—
TxInv
RxInv
MIR
—
SIR
IrDAEn
RESET
0
ADDRESS:
0x0F
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Resume3
Resume2
Resume1
Resume0
Halt3
Halt2
Halt1
Halt0
RESET
0
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