SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 28 Maxim Integrated Interrupt St" />
參數(shù)資料
型號(hào)： MAX3108EWA+T
廠商： Maxim Integrated Products
文件頁數(shù)： 21/56頁
文件大?。?/td> 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
28
Maxim Integrated
Interrupt Status Register (ISR)
The Interrupt Status register provides an overview of all interrupts generated by the MAX3108. Both the interrupt bits
and any pending interrupts on IRQ are cleared after reading ISR. When the MAX3108 is operated in polled mode, ISR
can be polled to establish the UART’s status. In interrupt-driven mode, IRQ interrupts are enabled by the appropriate
IRQEn bits. The ISR contents either give direct information on the cause for the interrupt or point to other registers that
contain more detailed information.
Bit 7: CTSInt
The CTSInt interrupt is generated when a logic state transition occurs at the CTS input. CTSInt is cleared after ISR is
read. The current logic state of the CTS input can be read out through the LSR[7]: CTSbit bit.
Bit 6: RFifoEmptyInt
The RFifoEmptyInt interrupt is generated when the receive FIFO is empty. RFifoEmptyInt is cleared after ISR is read.
Its meaning can be inverted by the MODE2[3]: RFifoEmptyInv bit.
Bit 5: TFifoEmptyInt
The TFifoEmptyInt interrupt is generated when the transmit FIFO is empty and the transmitter is transmitting the last
character. Use STSInt[7]: TxEmptyInt to determine when the last character has completed transmission. TFifoEmptyInt
is cleared after ISR is read.
Bit 4: TxTrgInt
The TxTrgInt interrupt is generated when the number of characters in the transmit FIFO is equal to or greater than the
transmit FIFO trigger level defined in FIFOTrgLvl[3:0]. TxTrgInt is cleared when the transmit FIFO level falls below the
trigger level or after ISR is read. TxTrgInt can be used as a warning that the transmit FIFO is nearing overflow.
Bit 3: RxTrigInt
The RxTrigInt interrupt is generated when the receive FIFO fill level reaches the receive FIFO trigger level defined in
FIFOTrgLvl[7:4]. RxTrigInt can be used as an indication that the receive FIFO is nearing overrun. It can also be used
to report that a known number of words are available that can be read out in one block. The meaning of RxTrigInt can
be inverted by the MODE2[2]: RxTrgInv bit. RxTrigInt is cleared after ISR is read.
Bit 2: STSInt
The STSInt interrupt is generated when any interrupt in the STSInt register that is enabled by a STSIntEn bit is high.
STSInt is cleared after ISR is read, but the interrupt in STSInt that caused this interrupt remains set. See the STSInt
register description for details about this interrupt.
Bit 1: SpCharInt
The SpCharInt interrupt is generated when a special character is received, a line break is detected, or an address
character is received in multidrop mode. SpCharInt is cleared after ISR is read, but the interrupt in SpclCharInt that
caused this interrupt remains set. See the SpclCharInt register description for details about this interrupt.
Bit 0: LSRErrInt
The LSRErrInt interrupt is generated when any interrupts in LSR that are enabled by corresponding bits in LSRIntEn
are set. This bit is cleared after ISR is read. See the LSR register description for details about this interrupt.
ADDRESS:
0x02
MODE:
COR
BIT
7
6
5
4
3
2
1
0
NAME
CTSInt
RFifoEmptyInt
TFifoEmptyInt
TxTrgInt
RxTrigInt
STSInt
SpCharInt
LSRErrInt
RESET
0
1
0
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