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參數(shù)資料
| 型號： | MAX3108EWA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
35
Maxim Integrated
MODE1 Register
Bit 7: IRQSel
Depending on the logic level of the IRQSel bit, IRQ has different meanings. After a hardware (POR and RST) or soft-
ware (MODE2{0} reset, the IRQSel bit is set low and, after a short delay, the IRQ output signals the end of the power-
up sequence. IRQ is low during power-up and transitions to high when the MAX3108 is ready to be programmed.
Set IRQSel high to enable interrupt driven operation after the power-up sequence. Essentially, IRQSel is a global
enable for all interrupts that acts in addition to the interrupt enable registers.
Bit 6: AutoSleep
Set the AutoSleep bit high to set the MAX3108 to automatically enter low-power sleep mode after a period of no activity
(see the Auto-Sleep Mode section). An interrupt is generated in STSInt[6]: SleepInt when the MAX3108 enters sleep
mode.
Bit 5: ForcedSleep
Set the ForcedSleep bit high to force the MAX3108 into low-power sleep mode (see the Forced-Sleep Mode section).
The current sleep state can be read out through the ForcedSleep bit, even when the UART is in sleep mode.
Bit 4: TrnscvCtrl
Set the TrnscvCtrl bit high to enable auto transceiver direction control mode. RTS automatically controls the transceiver’s
transmit/receive enable/disable inputs in this mode. RTS is logic-low so that the transceiver is in receive mode with the
transmitter disabled until the TxFIFO contains data available for transmission, at which point RTS is automatically set
logic-high before the transmitter sends out the data. Once the transmitter is empty, RTS is automatically forced low
again.
Setup and hold times for RTS with respect to the TX output can be defined through the HDplxDelay register. A trans-
mitter empty interrupt is generated in ISR[5] when the TxFIFO is empty.
Bit 3: RTSHiZ
Set the RTSHiZ bit high to three-state RTS.
Bit 2: TXHiZ
Set the TXHiZ bit high to three-state the TX output.
Bit 1: TxDisabl
Set the TxDisabl bit high to disable transmission. If the TxDisabl bit is set high during transmission, the transmitter com-
pletes sending out the current character and then ceases transmission. Data still present in the transmit FIFO remains
in the TxFIFO. The TX output is set to logic-high after transmission.
In auto transceiver direction control mode, TxDisabl is high when the transmitter is completely empty.
Bit 0: RxDisabl
Set the RxDisabl bit high to disable the receiver so that the receiver stops receiving data. All data present in the receive
FIFO remains in the RxFIFO.
ADDRESS:
0x09
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
—
AutoSleep
ForcedSleep
TrnscvCtrl
RTSHiZ
TXHiZ
TxDisabl
RxDisabl
RESET
0
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