SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 34 Maxim Integrated Status Inter" />
參數(shù)資料
型號: MAX3108EWA+T
廠商: Maxim Integrated Products
文件頁數(shù): 28/56頁
文件大?。?/td> 0K
描述: IC UART
產(chǎn)品培訓(xùn)模塊: Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
34
Maxim Integrated
Status Interrupt Register (STSInt)
Bit 7: TxEmptyInt
The TxEmptyInt interrupt is generated when both the TxFIFO is empty and the last character has completed transmis-
sion. TxEmptyInt is cleared after STSInt is read. TxEmptyInt generates an interrupt in ISR[2] if enabled by STSIntEn[7].
Bit 6: SleepInt
The SleepInt status bit is generated when the MAX3108 enters sleep mode. SleepInt is cleared when the MAX3108
exits sleep mode. This status bit is cleared when the clock is disabled and is not cleared by reading STSInt. SleepInt
generates an interrupt in ISR[2] if enabled by STSIntEn[6].
Bit 5: ClkReady
The ClkReady status bit is generated when the clock, the predivider, and the PLL have settled, signifying that the
MAX3108 is ready for data communication. The ClkReady bit only works with the crystal oscillator. It does not work
with external clocking through XIN.
ClkReady is cleared when the clock is disabled and is not cleared after STSInt is read. ClkReady generates an inter-
rupt in ISR[2] if enabled by STSIntEn[5].
Bit 4: No Function
Bits 3–0: GPIxInt
The GPIxInt interrupts are generated when a change of logic state occurs on the associated GPIO input. The GPIxInt
interrupts are cleared after STSInt is read. The GPIxInt interrupts generate an interrupt in ISR[2] if enabled by the cor-
responding bits in STSIntEn[3:0].
ADDRESS:
0x08
MODE:
R/COR
BIT
7
6
5
4
3
2
1
0
NAME
TxEmptyInt
SleepInt
ClkReady
GPI3Int
GPI2Int
GPI1Int
GPI0Int
RESET
0
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