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參數(shù)資料
| 型號： | MAX3108EWA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 24/56頁 |
| 文件大小： | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
30
Maxim Integrated
Line Status Register (LSR)
LSR contains all error information related to the word most recently read out from the RxFIFO through RHR. The LSR
bits are not cleared after LSR is read; these bits stay set until the next character is read out of RHR, with the exception
of LSR[1], which is cleared by reading either RHR or LSR. LSR also contains the current logic state of the CTS input.
Bit 7: CTSbit
The CTSbit bit reflects the current logic state of the CTS input. This bit is cleared when the CTS input is low and set
when it is high. Following a power-up or reset, the logic state of CTSbit depends on the state of the CTS input.
Bit 6: No Function
Bit 5: RxNoise
If noise is detected on the RX input during reception of a character, the RxNoise interrupt is generated for that charac-
ter. LSR[5] corresponds to the character most recently read from RHR. RxNoise is cleared after the character follow-
ing the “noisy character” is read out from RHR. RxNoise generates an interrupt in ISR[0] if enabled by LSRIntEn[5].
Bit 4: RxBreak
If a line break (RX input low for a period longer than the programmed character duration) is detected, a break character
is put in the RxFIFO and the RxBreak interrupt is generated for this character. A break character is represented by an
all-zeros data character. The RxBreak interrupt distinguishes a regular character with all zeros from a break character.
LSR[4] corresponds to the current character most recently read from RHR. RxBreak is cleared after the character fol-
lowing the break character is read out from RHR. RxBreak generates an interrupt in ISR[0] if enabled by LSRIntEn[4].
Bit 3: FrameErr
The FrameErr interrupt is generated when the received data frame does not match the expected frame format in length.
A frame error is related to errors in expected STOP bits. LSR[3] corresponds to the frame error of the character most
recently read from RHR. FrameErr is cleared after the character following the affected character is read out from RHR.
FrameErr generates an interrupt in ISR[0] if enabled by LSRIntEn[3].
Bit 2: RxParityErr
The RxParityErr interrupt is generated when the parity computed on the character being received does not match
the received character’s parity bit. LSR[2] indicates a parity error for the character most recently read from RHR.
RxParityErr is cleared when the character following the affected character is read out from RHR.
In 9-bit multidrop mode (MODE2[6] is logic 1) the receiver does not check parity and the 9th bit (address/data) is
stored in LSR[2].
RxParityErr generates an interrupt in ISR[0] if enabled by LSRIntEn[2].
Bit 1: RxOverrun
The RxOverrun interrupt is generated when the receive FIFO is full and additional data is received that does not fit into
the receive FIFO. The receive FIFO retains the data that it already contains and discards all new data. RxOverrun is
cleared after LSR is read or the RxFIFO level falls below its maximum. RxOverrun generates an interrupt in ISR[0] if
enabled by LSRIntEn[1].
Bit 0: RTimeout
The RTimeout interrupt indicates that stale data is present in the receive FIFO. RTimeout is set when all of the char-
acters in the RxFIFO have been present for at least as long as the period programmed into the RxTimeOut register.
ADDRESS:
0x04
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
CTSbit
—
RxNoise
RxBreak
FrameErr
RxParityErr
RxOverrun
RTimeout
RESET
X
0
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