SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 52 Maxim Integrated 6) The maste" />
參數(shù)資料
型號： MAX3108EWA+T
廠商： Maxim Integrated Products
文件頁數(shù)： 48/56頁
文件大小： 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
52
Maxim Integrated
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave address plus a read
bit (high).
8) The slave asserts an ACK on the data line.
9) The slave sends 8 data bits.
10) The master asserts an ACK on the data line.
11) Repeat 9 and 10 N-2 times.
12) The slave sends the last 8 data bits.
13) The master asserts a NACK on the data line.
14) The master generates a STOP condition.
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX3108 generate ACK bits. To generate
an ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (Figure 22). To generate a NACK, leave
SDA high before the rising edge of the ninth clock pulse
and leave it high for the duration of the ninth clock pulse.
Monitoring for NACK bits allows for detection of unsuc-
cessful data transfers.
Applications Information
Startup and Initialization
The MAX3108 can be initialized following power-up,
a hardware reset, or a software reset as shown in
Figure 23. To verify that the MAX3108 is ready for
operation after a power-up or reset in an interrupt-driven
operation, wait for the IRQ output to deassert.
In polled mode, repeatedly read a known register until
the expected contents are returned.
Figure 22. Acknowledge
Figure 23. Startup and Initialization Flowchart
NOT ACKNOWLEDGE
ACKNOWLEDGE
12
89
SDA
SCL
S
POWER-UP/
RST INPUT PULLED HIGH
IS IRQ HIGH?
OR
DIVLSB READ
SUCCESSFULLY
Y
N
CONFIGURE
CLOCKING
CONFIGURE
MODES
CONFIGURE
FIFO CONTROL
CONFIGURE
FLOW CONTROL
CONFIGURE
GPIOs
START
COMMUNICATION
ENABLE
INTERRUPTS
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