x
9.3
Operations of the Delayed Interrupt Module ..................................................................................... 250
CHAPTER 10 INTERRUPT CONTROLLER .................................................................... 251
10.1 Outline of the Interrupt Controller ...................................................................................................... 252
10.2 Block Diagram of the Interrupt Controller .......................................................................................... 253
10.3 Registers of the Interrupt Controller .................................................................................................. 254
10.3.1 Interrupt Control Register (ICR) ................................................................................................... 256
10.3.2 Hold Request Cancel Request Level Setting Register (HRCL) ................................................... 257
10.4 Priority Judgment .............................................................................................................................. 258
10.5 Return from Standby Mode (Stop or Sleep) ...................................................................................... 261
10.6 Hold Request Cancel Request .......................................................................................................... 262
10.7 Using the Hold Request Cancel Register (HRCR) ............................................................................ 263
CHAPTER 11 A/D CONVERTER ..................................................................................... 267
11.1 Outline of the A/D Converter ............................................................................................................. 268
11.2 Block Diagram of the A/D Converter ................................................................................................. 269
11.3 Registers of the A/D Converter ......................................................................................................... 270
11.3.1 Control Status Register (ADCS) .................................................................................................. 271
11.3.2 Data Register (ADCR) ................................................................................................................. 276
11.4 Operations of the A/D Converter ....................................................................................................... 277
11.5 Converted Data Protection Function ................................................................................................. 279
11.6 Notes on Using the A/D Converter .................................................................................................... 281
CHAPTER 12 UART ........................................................................................................ 283
12.1 Outline of UART ................................................................................................................................ 284
12.2 UART Block Diagram ........................................................................................................................ 285
12.3 Uart Registers ................................................................................................................................... 286
12.3.1 Serial Mode Register (SMR) ........................................................................................................ 287
12.3.2 Serial Control Register (SCR) ...................................................................................................... 289
12.3.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ..................................... 291
12.3.4 Serial Status Register (SSR) ....................................................................................................... 292
12.3.5 Communication Prescaler Control Register (CDCR) ................................................................... 294
12.4 UART Operation Modes and Clock Selection ................................................................................... 295
12.4.1 Asynchronous (Step-synchronous) Modes .................................................................................. 298
12.4.2 CLK Synchronous Mode .............................................................................................................. 299
12.5 UART Interrupts and Flag Setting Timings ....................................................................................... 301
12.6 Notes on Use with Example of UART Application ............................................................................ 304
CHAPTER 13 DMA CONTROLLER (DMAC) .................................................................. 307
13.1 Outline of the DMA Controller ........................................................................................................... 308
13.2 Block Diagram of the DMA Controller ............................................................................................... 309
13.3 Registers of the DMA Controller ....................................................................................................... 310
13.3.1 DMAC Control/Status Register (DMACS) - Channels 0 to 4 ....................................................... 311
13.3.2 DMAC Addressing/Transfer Count Register (DMACC) - Channels 0 to 4 ................................... 317
13.3.3 DMAC General Control Register (DMACR) ................................................................................. 320
13.3.4 DMAC Source/Destination Address Register Groups (DMASA, DMADA) .................................. 322
13.4 Operations of the DMA Controller ..................................................................................................... 323
13.4.1 Setting a Transfer Request .......................................................................................................... 325