xiv
Figure 4.5-17
Write Cycle Timings of the Ordinary DRAM Interface ............................................................ 176
Figure 4.5-18
Ordinary DRAM Read Cycle Timings 1 .................................................................................. 178
Figure 4.5-19
Ordinary DRAM Read Cycle Timings 2 .................................................................................. 179
Figure 4.5-20
Ordinary DRAM Read Cycle Timings 3 .................................................................................. 179
Figure 4.5-21
Ordinary DRAM Write Cycle Timings 1 .................................................................................. 180
Figure 4.5-22
Ordinary DRAM Write Cycle Timings 2 .................................................................................. 181
Figure 4.5-23
Ordinary DRAM Write Cycle Timings 3 .................................................................................. 181
Figure 4.5-24
Automatic Wait Cycle Timings of the Ordinary DRAM Interface ............................................. 182
Figure 4.5-25
DRAM Interface Timings 1 in High-speed Page Mode ........................................................... 183
Figure 4.5-26
DRAM Interface Timings 2 in High-speed Page Mode ........................................................... 184
Figure 4.5-27
DRAM Interface Timings 3 in High-speed Page Mode ........................................................... 185
Figure 4.5-28
DRAM Interface Timings 4 in High-speed Page Mode ........................................................... 186
Figure 4.5-29
Read Cycle Timings of the Single DRAM Interface ................................................................ 187
Figure 4.5-30
Write Cycle Timings of the Single DRAM Interface ................................................................ 188
Figure 4.5-31
Single DRAM Interface Timings .............................................................................................. 189
Figure 4.5-32
Read Cycle Timings of the Hyper DRAM Interface ................................................................ 190
Figure 4.5-33
Write Cycle Timings of the Hyper DRAM Interface ................................................................. 191
Figure 4.5-34
Hyper DRAM Interface Timings .............................................................................................. 192
Figure 4.5-35
CAS before RAS (CBR) Refresh Timings ............................................................................... 193
Figure 4.5-36
Automatic Wait Cycle Timings for CBR Refresh ..................................................................... 194
Figure 4.5-37
Self-refresh Timings ................................................................................................................ 194
Figure 4.5-38
Bus Privilege Release Timing ................................................................................................. 195
Figure 4.5-39
Bus Privilege Acquisition Timing ............................................................................................. 195
Figure 4.6-1
Timings of the Double-frequency Clock (16-bit bus, word read access) ................................ 197
Figure 4.6-2
Timings of the Single-frequency Clock (16-bit bus, word read access) .................................. 197
Figure 5.1-1
Basic I/O Port Configuration ................................................................................................... 204
Figure 6.2-1
Block Diagram of the 16-bit Reload Timer .............................................................................. 213
Figure 6.3-1
Registers of the 16-bit Reload Timer ...................................................................................... 214
Figure 6.4-1
Counter Activation and Operation Timings ............................................................................. 219
Figure 6.4-2
Underflow Operation Timings ................................................................................................. 220
Figure 6.5-1
Trigger Input Operation Timings ............................................................................................. 221
Figure 6.5-2
Gate Input Operation Timings ................................................................................................. 221
Figure 6.5-3
Output Pin Function (RELD=1, OUTL=0) ............................................................................... 222
Figure 6.5-4
Output Pin Function (RELD=0, OUTL=0) ............................................................................... 222
Figure 6.6-1
Counter Status Transition ....................................................................................................... 223
Figure 7.2-1
Block Diagram of the PPG Timer ............................................................................................ 227
Figure 7.3-1
Registers of the PPG Timer .................................................................................................... 228
Figure 7.4-1
PWM Mode Timing Chart (Retrigger disabled) ....................................................................... 233