Communications Processor (CP)
MOTOROLA
MC68302 USER’S MANUAL
4-93
character recognition and stripping is desired to be performed in software. The bit should
be set (or reset) within the time taken to receive the following data byte. When this bit is
reset, the BCS calculations exclude the latest fully received data byte. When RBCS is set,
the BCS calculations continue normally.
0 = Disable receive BCS
1 = Enable receive BCS
SYNF—Transmit SYN1–SYN2 or IDLE between Messages and Control the RTS Pin
0 = Send ones between messages; RTS is negated between messages. The BISYNC
controller can transmit ones in both NRZ and NRZI encoded formats.
1 = Send SYN1–SYN2 pairs between messages; RTS is always asserted.
ENC—Data Encoding Format
0 = Non-return to zero (NRZ). A one is a high level; a zero is a low level.
1 = Non-return to zero inverted (NRZI). A one is represented by no change in the level;
a zero is represented by a change in the level. The receiver decodes NRZI, but a
clock must be supplied. The transmitter encodes NRZI.
COMMON SCC MODE BITS—See 4.5.3 SCC Mode Register (SCM) for a description of the
DIAG1, DIAG0, ENR, ENT, MODE1, and MODE0 bits.
4.5.13.10 BISYNC Receive Buffer Descriptor (Rx BD)
The CP reports information about the received data for each buffer using BD. The Rx
BD is shown in Figure 4-32. The CP closes the current buffer, generates a maskable
interrupt, and starts to receive data into the next buffer after one of the following events:
Receiving a user-defined control character
Detecting an error
Detecting a full receive buffer
Issuing the ENTER HUNT MODE command
Figure 4-32. BISYNC Receive Buffer Descriptor
The first word of the Rx BD contains control and status bits.
E—Empty
0 = The data buffer associated with this BD has been filled with received data, or data
reception has been aborted due to an error condition. The M68000 core is free to
examine or write to any fields of this BD.
1 = The data buffer associated with this BD is empty. This bit signifies that the BD and
its associated buffer are available to the CP. After it sets this bit, the M68000 core
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OFFSET + 0
E
X
W
I
C
B
—
—
—
—
—
DL
PR
CR
OV
CD
OFFSET +2
DATA LENGTH
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
OFFSET +4
OFFSET + 6