System Integration Block (SIB)
3-38
MC68302 USER’S MANUAL
MOTOROLA
RST—Reset Timer
This bit performs a software reset of the timer identical to that of an external reset.
0 = Reset timer (software reset), includes clearing the TMR, TRR, and TCN.
1 = Enable timer
ICLK—Input Clock Source for the Timer
00 = Stop count
01 = Master clock
10 = Master clock divided by 16. Note that this clock source is not synchronized to the
timer; thus, successive timeouts may vary slightly in length.
11 = Corresponding TIN pin, TIN1 or TIN2 (falling edge)
FRR—Free Run/Restart
0 = Free run—timer count continues to increment after the reference value is reached.
1 = Restart—timer count is reset immediately after the reference value is reached.
ORI—Output Reference Interrupt Enable
0 = Disable interrupt for reference reached (does not affect interrupt on capture func-
tion)
1 = Enable interrupt upon reaching the reference value
OM—Output Mode
0 = Active-low pulse for one CLKO clock cycle (60 ns at 16.67 MHz)
1 = Toggle output
NOTE
After reset, the TOUT signal begins in a high state, but is not
available externally until the PBCNT register is configured for
this function.
CE—Capture Edge and Enable Interrupt
00 = Capture function is disabled
01 = Capture on rising edge only and enable interrupt on capture event
10 = Capture on falling edge only and enable interrupt on capture event
11 = Capture on any edge and enable interrupt on capture event
PS—Prescaler Value
The prescaler is programmed to divide the clock input by values from 1 to 256. The value
00000000 divides the clock by 1; the value 11111111 divides the clock by 256. The res-
olution of the timer varies directly with the size of the prescaler. In order to make smaller
adjustments to the timer as needed, the prescaler should be as small as possible (see
3.5.2.6 General Purpose Timer Example).
3.5.2.2 Timer Reference Registers (TRR1, TRR2)
Each TRR is a 16-bit register containing the reference value for the timeout. TRR1 and
TRR2 are memory-mapped read-write registers.