Signal Description
MOTOROLA
MC68302 USER’S MANUAL
5-15
These eight pins can be used either as NMSI1 in nonmultiplexed serial interface (NMSI)
mode or as an ISDN physical layer interface in IDL, GCI, and PCM highway modes. The in-
put buffers have Schmitt triggers.
Table 5-7 shows the functionality of each pin in NMSI, GCI, IDL, and PCM highway modes.
NOTES:
1. In IDL and GCI mode, SDS2 is output on the PA7 pin.
2. CD1 may be used as an external sync in NMSI mode.
3. RTS is the RTS1, RTS2, or RTS3 pin according to which SCCs are connected to the PCM highway.
RXD1/L1RXD—Receive Data/Layer-1 Receive Data
This input is used as the NMSI1 receive data in NMSI mode and as the receive data input
in IDL, GCI, and PCM modes.
TXD1/L1TXD—Transmit Data/Layer-1 Transmit Data
This output is used as NMSI1 transmit data in NMSI mode and as the transmit data output
in IDL, GCI, and PCM modes. TXD1 may be configured as an open-drain output in NMSI
mode. L1TXD in IDL and PCM mode is a three-state output. In GCI mode, it is an open-
drain output.
RCLK1/L1CLK—Receive Clock/Layer-1 Clock
This pin is used as an NMSI1 bidirectional receive clock in NMSI mode or as an input clock
in IDL, GCI, and PCM modes. In NMSI mode, this signal is an input when SCC1 is working
with an external clock and is an output when SCC1 is working with its baud rate generator.
The RCLK1 output can be three-stated by setting bit 12 in the CKCR register (see 3.9
Clock Control Register).
TCLK1/L1SY0/SDS1—Transmit Clock/PCM Sync/Serial Data Strobe 1
This pin is used as an NMSI1 bidirectional transmit clock in NMSI mode, as a sync signal
in PCM mode, or as the SDS1 output in IDL/GCI modes. In NMSI mode, this signal is an
input when SCC1 is working with an external clock and is an output when SCC1 is working
with its baud rate generator. The TCLK1 output can be three-stated by setting bit 13 in the
CKCR register (see 3.9 Clock Control Register).
Table 5-7. Mode Pin Functions
Signal Name
NMSI1
GCI
IDL
PCM
RXD1/L1RXD
TXD1/L1TXD
RCLK1/L1CLK
TCLK1/L1SY0
CD1/L1SY1
I
RXD1
TXD1
RCLK1
TCLK1
CD1
I
L1RXD
L1TXD
L1CLK
SDS1
L1SYNC
I
L1RXD
L1TXD
L1CLK
SDS1
L1SYNC
I
L1RXD
L1TXD
L1CLK
L1SY0
L1SY1
O
I/O
I/O
I
O
I
O
I
O
I
O
I
O
I
I
I
CTS1/L1GR
I
CTS1
I
L1GR
I
L1GR
RTS1/L1RQ
BRG1
O
O
RTS1
BRG1
O
O
GCIDCL
BRG1
O
O
L1RQ
BRG1
O
O
RTS
BRG1