參數(shù)資料
型號: MC68HC05F4FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 106/130頁
文件大?。?/td> 2089K
代理商: MC68HC05F4FB
MC68HC05F4
MOTOROLA
8-3
RESETS AND INTERRUPTS
8
8.2
Interrupts
The MCU can be interrupted by six different sources, ve maskable hardware interrupts and one
nonmaskable software interrupt:
External signal on the IRQ pin
Keyboard interrupt
Core timer interrupt
16-bit programmable timer interrupt
Low voltage interrupt (LVI) – EEPROM
Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared providing the
corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed. Figure 8-1 shows the interrupt processing
ow.
Note:
Power-on or external reset clears all interrupt enable bits thus preventing interrupts
during the reset sequence.
TPG
73
05F4Book Page 3 Tuesday, August 5, 1997 1:10 pm
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