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參數(shù)資料
| 型號(hào)： | MC68HC05F4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 49/130頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | MC68HC05F4FB |
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MC68HC05F4
MOTOROLA
2-3
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.3
System options register
The MC68HC05F4 MCU contains a system options register which is located at address $11. This
register is used to control the LVI and the clock system.
Note:
The LVI uses the voltage reference of the low voltage reset (LVR) circuitry. This means
that the LVI can only be used if the LVR is enabled by mask option.
LVIF — Low voltage interrupt ag
1 (set)
–
A low voltage interrupt has occurred.
0 (clear) –
No low voltage interrupt has occurred.
LVIF is a read only status bit and is set by the low voltage detection circuit, if power supply VDD
falls below Vlvi, provided the LVR is enabled (mask option) and the LVION and LVIE bits are set.
The LVIF ag is reset by clearing the LVIE bit. The LVI circuit is rearmed by again setting the LVIE
bit.
LVIE — Low voltage interrupt enable
1 (set)
–
Low voltage interrupt and ag generation is enabled.
0 (clear) –
Low voltage interrupt and ag generation is disabled.
Setting this bit enables the low voltage ag and interrupt generation. A CPU interrupt request will
then be generated whenever the LVIF bit becomes set and the l-bit in the CCR is clear.
LVION — Low voltage interrupt on
1 (set)
–
Power is supplied to the LVI circuitry.
0 (clear) –
LVI circuitry is disconnected from the power supply.
Setting this bit applies power to the LVI circuitry. If the LVI function is not used this bit should be
cleared to save power.
Note:
This bit must be set at least one instruction cycle before setting the LVIE bit, to give the
LVI circuitry time to stabilize.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System options register (SOR)
$0011
LVIF
LVIE
LVION
SC
IRQ
0
0000 0000
TPG
21
05F4Book Page 3 Tuesday, August 5, 1997 1:10 pm
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