參數(shù)資料
型號(hào): MC68HC05F4FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 75/130頁
文件大?。?/td> 2089K
代理商: MC68HC05F4FB
MC68HC05F4
MOTOROLA
5-5
CORE TIMER
5
5.3
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output of the RTI circuit and
further dividing it by eight, as shown in Figure 5-1. Note that the minimum COP timeout period is
seven times the RTI period. This is because the COP will be cleared asynchronously with respect
to the value in the core timer counter register/RTI divider, hence the actual COP timeout period
will vary between 7x and 8x the RTI period. The minimum COP reset rates are shown in Table 5-2.
The COP function is a mask option, enabled or disabled during device manufacture.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
A COP timeout is prevented by writing a ‘0’ to bit 0 of address $3FF0. When the COP is cleared,
only the nal divide-by-eight stage is cleared (see Figure 5-1).
5.4
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the timer remains active. If the CTIMER interrupts
are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (tPORL). The timer is then cleared and operation resumes.
Table 5-2 Minimum COP reset times
Minimum COP reset at fOP frequency specied
RT1
RT0
16.384 kHz
447 kHz
895 kHz
1.789 MHz
fOP
0
7 s
256.9 ms
128.45 ms
64.19 ms
7 x RTI rate
0
1
14 s
513.8 ms
256.9 ms
128.45 ms
7 x RTI rate
1
0
28 s
1.03 s
513.8 s
256.9 ms
7 x RTI rate
1
56 s
2.06 s
1.03 s
513.8 ms
7 x RTI rate
TPG
45
05F4Book Page 5 Tuesday, August 5, 1997 1:10 pm
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